FPGA source code for bit file - LibreSDR

[SV8ARJ]

Dear Evariste, All, hi.
Can someone verify (or correct) the folllowing points ?

• When compiling with buildroot (for libreSDR) the FPGA bit file is from system_top.xsa in board/tezuka/libre/bitstream/maia-iio
• The PLL/Reference correction loop is implemented in https://github.com/F5OEO/maia-sdr/tree/sweep/maia-hdl/libresdr-hdl
• This file's source for tezuka v0.2.0 is from https://github.com/F5OEO/maia-sdr/tree/sweep (attention on the sweep branch)

Also, what are the adddresses for dac_mode and dac_user_set_value (for devmem use)
Cheers !

[F5OEO]

• When compiling with buildroot (for libreSDR) the FPGA bit file is from system_top.xsa in board/tezuka/libre/bitstream/maia-iio
  Yes, for as Vivado is not always installed, bitsreams are placed here, built by the step maia-sdr
• The PLL/Reference correction loop is implemented in https://github.com/F5OEO/maia-sdr/tree/sweep/maia-hdl/libresdr-hdl
  Yes..that's a first attempts still in progress..I could test it as I receive the original libresdr
• This file's source for tezuka v0.2.0 is from https://github.com/F5OEO/maia-sdr/tree/sweep (attention on the sweep branch)
  Yes

Also, what are the adddresses for dac_mode and dac_user_set_value (for devmem use) Cheers !
See https://wiki.analog.com/resources/fpga/docs/axi_ad9361