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San Jose State University
- San Jose, California
- https://www.linkedin.com/in/harshil-patel-msee-60a33b177/
- @Harshil36472760
Popular repositories Loading
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I2C_UVM_APB
I2C_UVM_APB PublicFormulated testbench using System Verilog and UVM and verified I2C bus controller with APB interface
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Spread-Spectrum-Correlator
Spread-Spectrum-Correlator PublicThe aim of this project is to recover a signal using correlator that was spread with a Gold code using Phase Shift Keying. So, to do so. we built a unit that runs on 333MHz Frequency which accepts …
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FPGA_Vending-Machine-uisng-Verilog
FPGA_Vending-Machine-uisng-Verilog Public• Built RTL for Vending Machine on FPGA board that accepts money, selects an item and gives out the change. Four 7-segment display employed for displaying product price and selection.
Verilog 1
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FPGA_Traffic-Light-Controller-using-verilog
FPGA_Traffic-Light-Controller-using-verilog PublicConstructed RTL for traffic light control system for multiple intersections supporting pedestrian signals on FPGA board.
Verilog 1
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AXI4LITE_UVM_AHB
AXI4LITE_UVM_AHB PublicExecuted a Bus Functional Model using RTL design for the AXI4 LITE to AHB Bridge using System Verilog. Implemented verification for protocol based serial transaction from both ends of bridge using …
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