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Physical p‐bit Hardware Prototype
The goal is to build a small hardware p-bit computer containing at least 8 independent natural physical p-bits, where stochastic behavior is generated by real electronic noise rather than a software PRNG, and connect it to a PC over USB. The design is simple enough to be built at home as a proof-of-concept using readily available components, with device-to-device variations compensated through software calibration using MCU (microcontroller), such as an ESP32 or RP2350.
The project now has its homepage: https://github.com/toncho11/probana
Each p-bit uses a physical electronic noise source followed by amplification and a comparator. A controllable bias voltage changes the probability of the output being 0 or 1:
A microcontroller controls the bias voltages through a multi-channel DAC and reads the digital p-bit outputs.
Real p-bits will not be identical. Each channel may have a different offset, gain and noise distribution.
During calibration, the controller sweeps the bias of each p-bit and measures its output probability:
The resulting probability curve is stored as a calibration table. During operation, a requested p-bit probability or p-kit bias is converted back into the voltage required by that particular physical p-bit.
Calibration could also measure:
- actual zero-bias probability
- temporal autocorrelation;
- cross-correlation between different p-bits;
- drift with time and temperature.
This allows imperfect discrete noise devices to behave approximately like calibrated p-bits and provides a small physical hardware backend for IBM p-kit.
Schematic 1
+------------------------------------------------------------------+
| USB / CONTROL SECTION |
| |
| USB-C |
| +-----+ |
| | USB |----+ |
| +-----+ | |
| v |
| +-------------+ +-------------+ +---------------+ |
| | MCU / USB |------->| 8-ch DAC |<--| 2.5 V REF | |
| | RP2040 etc. | SPI | | | (optional) | |
| +-------------+ +-------------+ +---------------+ |
| ^ | | | | | | | | |
| | digital inputs | | | | | | | | bias voltages |
| | v v v v v v v v |
| | VBIAS0 ... VBIAS7 ----to-p bits----->|
| | |
| +------------- from p-bit outputs -- Q0 ... Q7 ------+
| |
+------------------------------------------------------------------+
VBIAS0 ... VBIAS7 are analog voltages generated by the DAC. Each VBIAS controls the probability of its corresponding physical p-bit output being 0 or 1.
Schematic 2
+---------------------------------------------------+
| PHYSICAL P-BIT SECTION |
| |
| +------------------+ |
| | [P-BIT 0] | |
| | | |
| | Noise source | |
| | ↓ | |
| | Amplifier | |
| | ↓ | |
| VBIAS0 ----->| Comparator | |
| | ↓ | |
| | Q0 | |
| +------------------+ |
| |
| . |
| . |
| . |
| |
| +------------------+ |
| | [P-BIT 7] | |
| | | |
| | Noise source | |
| | ↓ | |
| | Amplifier | |
| | ↓ | |
| VBIAS7 ----->| Comparator | |
| | ↓ | |
| | Q7 | |
| +------------------+ |
| |
| Q0 ... Q7 ---------------------------> MCU inputs |
+---------------------------------------------------+
For the basic 8-p-bit board, the MCU has about 5 main jobs:
- Communicate with the PC over USB
- Set
VBIAS0 ... VBIAS7through the DAC - Read
Q0 ... Q7digital p-bit outputs - Calibrate each p-bit by sweeping
VBIASand measuringP(1) - Apply the calibration so a requested probability or bias is converted to the correct DAC voltage
Later:
-
Run the p-kit update loop locall by computing
[ I_i = h_i + \sum_j J_{ij} m_j ]
then set the corresponding bias voltages, sample the physical p-bits, and repeat.
- we can combine these 8 physical p-bits with 56 p-bits emulated on the MCU and study how the circuit’s performance changes compared to a fully emulated implementation