Update cache with latest Py2HWSW#320
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jjts merged 24 commits intoIObundle:mainfrom Oct 9, 2025
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Create Py2 modules for cache subblocks.
Since always @ blocks check on posedge of the reset signal, then the reset is an asynchronous reset.
Similar implementation to the one in iob-soc. When new releases of iob-cache are created, this workflow will generate two tar.gz files (with BE_IF=AXI4 and BE_IF=IOb) and upload them as release assets.
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Pull Request Overview
This PR updates the iob-cache project to use the latest version of Py2HWSW, which includes significant fixes and architectural improvements. The main changes include transitioning to a new modular architecture with multiple configuration modules, updating documentation and build processes, and adding release artifact generation.
- Updates to the latest Py2HWSW version with improved modular architecture
- Migrates from monolithic Verilog files to separate configuration modules
- Adds release artifact generation for pre-built tar.gz files
Reviewed Changes
Copilot reviewed 27 out of 32 changed files in this pull request and generated no comments.
Show a summary per file
| File | Description |
|---|---|
| iob_cache.py | Core module definition updated to use new Py2HWSW modular architecture with separate subblocks |
| hardware/src/iob_cache_*.v | Removed monolithic Verilog files, replaced by modular approach |
| hardware/simulation/src/ | Updated testbench and simulation wrapper for new architecture |
| hardware/modules/ | New modular subblock definitions for front-end, back-end, memory, and control |
| default.nix | Updated Py2HWSW version and improved Nix configuration |
| README.md | Enhanced documentation with setup instructions and pre-built file information |
| Makefile | Improved build system with better parameter handling and release artifact generation |
| .github/workflows/release-artifacts.yml | New workflow for automated release artifact generation |
Comments suppressed due to low confidence (1)
hardware/modules/iob_cache_memory/hardware/src/iob_cache_memory.v:1
- The bit range selection changed from 'addr_reg_i[FE_NBYTES_W +: WORD_OFFSET_W]' to 'addr_reg_i[0 +: WORD_OFFSET_W]'. This could be a significant logic change - verify this is correct for the new address mapping scheme.
// SPDX-FileCopyrightText: 2024 IObundle
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P-Miranda
approved these changes
Oct 9, 2025
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Update iob-cache with latest version of py2hwsw (including fixes in PR IObundle/py2hwsw#395).
Update README.
Add release-artifacts workflow to generate tar.gz files with pre-built build dirs.