CaCCon

README generated by Copilot! (few manual edits though)

Introduction

This project models a 4-way set associative 16KB cache memory with PLRUt (Pseudo-Least Recently Used (tree variant)) based cache replacement policy along with 8MB RAM. There is also a cache controller to manage memory access, coordinate cache hits and misses and implement the PLRUt eviction logic.

Cache Structure

• Number of Sets: 64 (since 16KB / (4 ways * 64 bytes/block))
• Block Size: 64 bytes
• Total Cache Size: 16KB

PLRUt Replacement Policy

The PLRUt (Pseudo-LRU with Time) replacement policy is employed to manage cache evictions. This policy tracks usage patterns to determine which cache lines to replace, thereby optimizing performance and minimizing cache misses.

Key Features of PLRUt:

• Implements a pseudo-LRU mechanism to reduce overhead.
• Considers temporal usage patterns to enhance data retention.

Main Memory Interface

The Cache Controller communicates with the main memory through a dedicated interface that handles requests for data fetch and write-back operations.

Interface Protocol:

1. Read Requests: Initiates a read operation from main memory.
2. Write Requests: Sends data to be updated in main memory.

Module Descriptions

• Cache Memory Module: Stores data in the cache with fast access times.
• Control Logic Module: Manages cache operations, including reading, writing, and replacement policy enforcement.
• Interface Logic Module: Handles communication between the cache controller and the main memory.

FSM States

The Finite State Machine (FSM) governs the behavior of the cache controller. The operational states include:

• Idle: Waiting for a request.
• Read: Processing a read request.
• Write: Processing a write request.
• Evict: Replacing a cache line based on the PLRUt policy.

Signal Interfaces

Signal interfaces control the interactions between various modules:

• Read Signal: Indicates a cache read request is in progress.
• Write Signal: Indicates a cache write request is active.
• Evict Signal: Activates when a cache line needs to be replaced.

Operation Flow

1. Input Detection: The cache controller detects an incoming read or write request.
2. Cache Lookup: Checks if the data exists in the cache.
3. Data Handling:
   • If present, the data is returned to the requester.
   • If not present, a read operation to main memory is initiated, and the data is loaded into the cache, possibly evicting an existing line based on the PLRUt policy.

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Updated on 2026-04-15 15:11:38 UTC