Repository navigation
This version includes:
- Stages Modularization: Division into independent modules for greater clarity and ease of use.
- Wishbone protocol for memory and peripherals: Unified bus with addresses above
0x7FFF_FFFFreserved for peripherals. - Verified MDU: All critical calculations and operations have been tested and confirmed.
- Support for FPGA Open Source SDR Lab (Kintex 7).
- New UART implementation with configurable bitrate and parity configuration.
- Improved Firmware:
- Enhanced functions for UART, data conversion, and delay.
- Now it's possible to configure new UART parameters directly in the firmware.
- Custom CSR register with Core operating frequency
Contributions are welcome!