GKD Pixel2 - Alpha 1.4 - Sleep+GPU+Display Fixes

Alpha 1.4. Follows up on Alpha 1.3.

Since Alpha 1.3:

Suspend-to-memory (deep sleep) is now fully supported, and files have been updated from yesterday in-place. See below for more details. Other changes include:

• Fixed a real display corruption bug on wake from freeze/idle suspend: the panel driver's unprepare() used to abort its entire power-down sequence if a single DSI command failed mid-suspend, leaving the panel powered with a stale frame and permanently stuck (since the next prepare() would then also no-op). It now always completes the power-down regardless of DSI command success.
• Fixed the underlying timing cause of that corruption: the panel's prepare/reset GPIO sequencing had too little settling time before its DCS init sequence started. Mirrored the more conservative timings (prepare 2->20ms, reset 1->150ms) from this board's earlier ST7701 driver approach, which resolved it on real hardware.
• Closed a gap in the PX30S GPU power-domain clock-ownership workaround: rockchip_pd_power()'s own clock enable/disable pair was still touching SCLK_GPU independently of mali_kbase's own clock ownership, confirmed via a live pstore/ramoops capture to be oopsing inside disable_gpu_power_control().
• Fixed an FPS drop right after suspend/resume from freeze/idle: mali_kbase's resume path wasn't waiting for its own devfreq-resume work to complete before returning, so rendering could resume before the GPU's DVFS governor actually restarted - the GPU could be left at a stale, low frequency while already being asked to render.

Suspend-to-memory (deep sleep) is now fully supported. The post-resume-from-deep-suspend crash on the first dynamic CPU governor transition (ondemand/schedutil), previously an open issue in this cycle, has been root-caused and fixed. This cycle ruled out a long list of candidate causes with real evidence rather than guesswork: CPU/GPU OPP table voltage values (confirmed correct against vendor's actual binding documentation and reference px30.dtsi, bit-for-bit), the SIP suspend/wakeup-config values sent to BL31 firmware (also confirmed correct against vendor's own reference implementation), and the firmware suspend-config handshake itself (a real hardware test of removing it broke resume outright, confirming it's required, not the cause). The actual cause: drivers/clk/rockchip/clk-px30.c never saved or restored PX30_MODE_CON (PLL slow/normal mode select) or PX30_CLKSEL_CON(0) (the CPU core clock divider) across suspend/resume - unlike clk-rk3288.c, which already has an equivalent mechanism for the same class of bug on a sibling SoC, where the SoC's own resume path resets certain CRU registers independent of Linux. The next CPU frequency change after resume was building its safe-switch sequence on that stale/reset register value instead of what Linux had actually configured, corrupting memory. Fixed by porting rk3288's save/restore mechanism to PX30/PX30S. Confirmed fixed on real hardware.

Build artifacts: refreshed to a build including the suspend-to-memory fix above (-b image and .tar only).