Red Sky Instruction Set Architecture

Registers

By default, the CPU has 8 32 bit registers: r0 - r7. r0 is used by the push and pop instructions as a stack pointer. It also has 4 8 bit input ports (in0 - in3) and 4 8 bit output ports (out0 - out3).

CAsm: C-Style Assembly

CAsm is a high-level assembly language with a syntax based on the C language. The result is a language familiar to most programmers, but with fine grained control of object code. Most CAsm statements map to a single instruction, as is expected from an assembly language. However, being an HLA, some statements (such as if's and else's) expand into to multiple instructions.

Assignment

_register_ **=** (_register_ | _const32_)**;**

Example

r1 = 0xdeadbeef;
r2 = r1;

Add

_register_ **+=** (_register_ | _const32_)**;**

Example

r1 += 0xdeadbeef;
r2 += r1;

Subtract

_register_ **-=** (_register_ | _const32_)**;**

Example

r1 -= 0xdeadbeef;
r2 -= r1;

Multiply

_register_ ***=** (_register_ | _const32_)**;**

Example

r1 *= 0xdeadbeef;
r2 *= r1;

Increment

_register_ **++;**

Example

r1++;
r2++;

Decrement

_register_ **--;**

Example

r1--;
r2--;

Data

**data(** _string_ **);**

Example

data("foo\x00");
data("bar\x00");

Label

_identifier_ **;**

Example

foo;
    data("foo\x00");

bar;
    data("bar\x00");

Read Memory

_register_ **=** ( ( *****_register_ ) | ( ***(**_register_ **+** _const16_ **)** ) ) **;**

Example

r1 = *r3;
r2 = *(r3 + 0x4);

Write Memory

( ( *****_register_ ) | ( ***(**_register_ **+** _const16_ **)** ) ) **=** ( _register_ | _const32_ ) **;**

Example

*r3 = r1;
*(r3 + 0x4) = r2;

Condition

_register_ ( (**==**) | (**!=**) | (**<**) | (**<=**) | (**>**) | (**>=**) ) ( _register_ | _const32_ ) **;**

Example

r1 == r2;
r1 < r2;
r2 <= 0xdeadbeef;

Goto

(**goto** | **gotoTrue** | **gotoFalse**) **(** ( _const32_ | _label_ ) **);**

Example

r1 = 0x10;

loop1;
    r1--;
    r1 == 0;
    gotoFalse(loop1);
    
loop2;
    r1++;
    goto(loop2);

If/Else

**if (**_condition_**)** _body_ [ **else** _body_ ]

Example

if (r1 == 0xdeadbeef) {
    /* do stuff */
} else {
    /* do other stuff */
}

For

**for (**_initialization_**;** _condition_**;** _afterthought_**)** _body_

Example

for (r1 = 0; r1 < 4; r1++) {
    /* do stuff */
}

While

**while (**_condition_**)** _body_

Example

while (r1 < 100) {
    /* do stuff */
}

Opcodes

Opcode	Instruction
01	Push_Const
0A	SetOut0_Const
0B	SetOut1_Const
0C	SetOut2_Const
0D	SetOut3_Const
10	Add_R0_C
11	Add_R1_C
12	Add_R2_C
13	Add_R3_C
14	Add_R4_C
15	Add_R5_C
16	Add_R6_C
17	Add_R7_C
18	Sub_R0_C
19	Sub_R1_C
1A	Sub_R2_C
1B	Sub_R3_C
1C	Sub_R4_C
1D	Sub_R5_C
1E	Sub_R6_C
1F	Sub_R7_C
20	Mul_R0_C
21	Mul_R1_C
22	Mul_R2_C
23	Mul_R3_C
24	Mul_R4_C
25	Mul_R5_C
26	Mul_R6_C
27	Mul_R7_C
28	Div_R0_C
29	Div_R1_C
2A	Div_R2_C
2B	Div_R3_C
2C	Div_R4_C
2D	Div_R5_C
2E	Div_R6_C
2F	Div_R7_C
30	And_R0_C
31	And_R1_C
32	And_R2_C
33	And_R3_C
34	And_R4_C
35	And_R5_C
36	And_R6_C
37	And_R7_C
38	Or_R0_C
39	Or_R1_C
3A	Or_R2_C
3B	Or_R3_C
3C	Or_R4_C
3D	Or_R5_C
3E	Or_R6_C
3F	Or_R7_C
40	Assign_R0_Const
41	Assign_R1_Const
42	Assign_R2_Const
43	Assign_R3_Const
44	Assign_R4_Const
45	Assign_R5_Const
46	Assign_R6_Const
47	Assign_R7_Const
48	Eq_R0_C
49	Eq_R1_C
4A	Eq_R2_C
4B	Eq_R3_C
4C	Eq_R4_C
4D	Eq_R5_C
4E	Eq_R6_C
4F	Eq_R7_C
50	NotEq_R0_C
51	NotEq_R1_C
52	NotEq_R2_C
53	NotEq_R3_C
54	NotEq_R4_C
55	NotEq_R5_C
56	NotEq_R6_C
57	NotEq_R7_C
58	LessThan_R0_C
59	LessThan_R1_C
5A	LessThan_R2_C
5B	LessThan_R3_C
5C	LessThan_R4_C
5D	LessThan_R5_C
5E	LessThan_R6_C
5F	LessThan_R7_C
60	LessThanEq_R0_C
61	LessThanEq_R1_C
62	LessThanEq_R2_C
63	LessThanEq_R3_C
64	LessThanEq_R4_C
65	LessThanEq_R5_C
66	LessThanEq_R6_C
67	LessThanEq_R7_C
68	GreaterThan_R0_C
69	GreaterThan_R1_C
6A	GreaterThan_R2_C
6B	GreaterThan_R3_C
6C	GreaterThan_R4_C
6D	GreaterThan_R5_C
6E	GreaterThan_R6_C
6F	GreaterThan_R7_C
70	GreaterThanEq_R0_C
71	GreaterThanEq_R1_C
72	GreaterThanEq_R2_C
73	GreaterThanEq_R3_C
74	GreaterThanEq_R4_C
75	GreaterThanEq_R5_C
76	GreaterThanEq_R6_C
77	GreaterThanEq_R7_C
78	LeftShift_R0_C
79	LeftShift_R1_C
7A	LeftShift_R2_C
7B	LeftShift_R3_C
7C	LeftShift_R4_C
7D	LeftShift_R5_C
7E	LeftShift_R6_C
7F	LeftShift_R7_C
80	RightShift_R0_C
81	RightShift_R1_C
82	RightShift_R2_C
83	RightShift_R3_C
84	RightShift_R4_C
85	RightShift_R5_C
86	RightShift_R6_C
87	RightShift_R7_C
88	Xor_R0_C
89	Xor_R1_C
8A	Xor_R2_C
8B	Xor_R3_C
8C	Xor_R4_C
8D	Xor_R5_C
8E	Xor_R6_C
8F	Xor_R7_C
E0	Call_Const
E2	Goto_Const
E5	Goto_Eq
E6	Goto_NotEq
FB	Ext
FD	ExtMultiStage
FF	Error
Sub Opcodes 1
01	Assign
20	Inc_R
21	Dec_R
50	Eq_R_R
51	NotEq_R_R
52	LessThan_R_R
53	LessThanEq_R_R
54	GreaterThan_R_R
55	GreaterThanEq_R_R
F0	In
F1	Out
Sub Opcodes 2
01	Push_R
02	Pop_R
10	Read
11	Write
20	Add_R_R
21	Sub_R_R
22	Mul_R_R
23	Div_R_R
24	And_R_R
25	Or_R_R
26	Xor_R_R
30	LeftShift_R_R
31	RightShift_R_R
E0	Call_R
F0	Return