-
Notifications
You must be signed in to change notification settings - Fork 2
Home
Welcome to the SST-6809 wiki!
The SST (Super Searle-Tranter) board is a 10cm by 10cm single board computer using either the MC6809 or the HD6309 microprocessor. It provides the resources needed to run and communicate with an attached support computer such as a PC or laptop. The present design employs traditional technology such as through hole mounted components, and MSI logic IC’s in the 74HCT logic family. Denser and more affordable memory was used, than in the era of introduction of the MC6809. Thus it suggests, a computer that could have been made in the 1980’s, if advanced memory devices were available. Like the Searle-Tranter design, an expansion bus is provided. But in this case, the bus has been enhanced and expanded to provide more flexibility and options.
The CPU, either MC6809 or HD6309, extends its data, address and control signals directly to the expansion bus. The data and address lines also extend to the on board EEPROM and NVRAM IC’s, and the MC6850 or HD6350 ACIA serial communications IC. Some of the address and control lines also extend to a cluster of decode circuitry, which controls both the on board components and the expansion bus control lines. There are no bus buffers on the expansion bus, both for the reason of simplicity, and also because the facilities of the board may be extended via the bus connector, to an external CPU so that it can make use of them (when the CPU socket is depopulated).
The operation of the CPU is straightforward and is explained in the Motorola documentation. The expansion bus is MC6809 oriented and so, directly exposes the most important control signals of the processor to peripheral cards that are connected to it. A few of the bus signals are unique, and those will be explained later on. On the board, the decode logic selects and provides the correct timing signals to the memory, ACIA and paging latch. Generally, the memory map consists of mostly non-volatile SRAM that is battery backed up via a NVRAM controller IC. The memory allocation of both the I/O and the EEPROM occupy only 4kb each, so that 56kb of contiguous RAM is available to loaded software. Both the EEPROM and the NVRAM size exceed what can fit in an 8 bit CPU’s memory, so those are paged using a latch that can be controlled by the CPU. The current NVRAM is 512kb in size, and the EEPROM is 32kb. Because the main memory is non-volatile, programs under development need not be repetitively loaded for testing, working programs may not need auxiliary memory, and the remaining 460kb of NVRAM may be used for paged executable software, or as a RAM based disk drive emulation.
As mentioned, the CPU U1 coordinates all bus activity via its data, address, and control lines. The CPU is driven by an on chip clock oscillator controlled by quartz crystal Y1. The CPU signal E which sets bus timing, is derived from the oscillator, at 1/4 the frequency of that crystal. Thus, an 8.0MHz crystal will run the bus at 2.0MHz. The allowable frequency depends on the timing specifications of the specific CPU in use, as well as all the other devices on the bus. The main CPU control signals that are used on board are E (bus enable), R/W (read/write), and RESET. Interrupt line IRQ also extends to the ACIA for interrupt driven serial operation. Most of the CPU control lines also extend to the external bus interface connector. Thus external DMA, slow memory accesses, etc., are supported on the bus.
The EEPROM functions as a boot and monitor ROM, and occupies the uppermost 4kb of CPU memory space. Because it is actually a 32kb device, a particular bank of 4kb can be made active using a combination of software settings and jumper settings. Normally, it will boot from the default bank that is selected with the on board jumpers. Booting, loading binary code, and simple debugging using the monitor, is all that it usually does. The bank selection is performed using a memory mapped latch U2 that is shared with the NVRAM banking scheme.
The SRAM socket may hold either a 128kb or 512kb NVRAM, and is also bank selected with a combination of latch U2 and a special “steering” gate U6A. The purpose of U6A is to enforce a contiguous 56k CPU view of main memory, while also supporting the swapping of 32k pages in the lower half of memory. This is done with NOR gate U6A.
Without U6A, either the lower 32k would be duplicated in the upper 32k of memory, or else the paging would be restricted to 64k pages. That would conceal the 8k at the high end of each extended memory page, which is an unacceptable waste. Unfortunately, U6A by itself is not sufficient to maintain a static mapping of the upper 32kb of memory, so paging must be performed by routines resident in ROM only. This limitation will be addressed in future versions.
Paging latch U2 may be written by the CPU to select different segments of the extended EEPROM and NVRAM memory. It controls both, the lower 4 bits control NVRAM, 3 upper bits control EEPROM page selection, and one remaining bit controls a status display LED on the board. Due to the aim for simplicity, the latch location is not qualified with the R/W signal, which means that if it is read instead of written, random data will be written to the latch. This will usually crash the machine. Again, this will be corrected in future board designs.
This NOR gate inverter simply inverts a memory address, in such a way that a 128kb device can operate in the same socket as a 512kb device.
The MC6850/HD6350 is a complete asynchronous serial interface, which enables serial communication with external serial devices. It obtains its timing reference from a 1.8432MHz crystal oscillator module on board. A mounting space has been provided on board, to attach a USB/serial conversion module to the serial lines, so that the board can communicate directly with a USB host running the serial protocol. The operating power for the board can optionally come from there, or else from a dedicated power connector J2 adjacent to it. The MC6850 was designed by Motorola, specifically for use with Motorola 8 bit CPU’s, so the rest of the interface details are unremarkable. It is mapped into the I/O space by the decode circuit on board.
DS1813 is the preferred reset device, and will hold the CPU and any attached peripherals in a RESET state when power is applied or removed. Two alternate circuits are provided on board, in case the component can’t be obtained. A short to ground will activate the DS1813, so the reset button uses that method to perform a manual reset. Decoding Circuit Note: The address and control decoding is performed separately from the timing clock signal E. That is to eliminate setup and hold requirement compromises at the inputs of the peripherals that the decode circuit is controlling. So, it will be apparent that the E signal is combined with the decoded address and control signals, at the last possible stage in the decoding circuit.
3 input to 8 line selector U10, a 74HCT138 IC, is configured to activate one of eight output lines, each one spanning a 4kb segment of the upper 32kb of memory. The uppermost line selects the ROM in $F000-$FFFF. The remaining 7 lines go to a header block, so that the 4kb I/O segment location can be jumper selected. For the maximum contiguous RAM, it would be set to $E000-$EFFF and so that is considered a default.
This half of dual selector 74HCT139, performs two functions at the same time. It separates RAM and ROM memory accesses, and also performs the conversion of Motorola standard E and R/W based bus timing, to the separate read and write signals that the memory devices use. U13A This NAND gate decodes some important memory control signals and passes them to U8B. As it is the second to last stage before driving memory, the E signal is included. The DIS signal is include so that memory can be disabled for external bus overlays.
The other half of U8 further divides the I/O block into two on board, and two external bus decodes.
This circuit portion further decodes the address and qualifies the input to the memory paging latch U2 with the timing signal E.
The DS1210 Non volatile memory controller IC connects the on board 3.0V coin cell, to the SRAM IC power pin, and also safeguards the SRAM accesses by disabling the control input CS on the SRAM, unless it detects that the supply voltage indicates that the system is powered on. Otherwise, the SRAM contents could be corrupted by the random bus states that the CPU circuit assumes when it is undergoing a power application or removal.
This gate parallels a ROM bank select jumper setting so that it can be both manually and jumper controlled. It will be deprecated in future.