Resistor 0.22.0 · SAR ADC and bounded chip layouts

8-bit charge-redistribution SAR with eight editable blocks, real ngspice comparator decisions and RTL / synthesized-gate / CMOS graph replay. New physical templates fold PCells into a configurable chip envelope; out-of-bounds edits and imports are rejected before revision commit. Existing designs are retained.

Eight bounded references completed 40/40 native DRC/LVS/PEX/pre/post checks at TT/27°C/1.8V, typical RC. All 256 static bin centers plus directed boundaries: 259 inputs, zero pre-layout code error. Post-layout SAR meets ±1 code with unambiguous comparator levels; ENOB is unmeasured. 73 native regressions and 161 core tests passed.

Exact Apple Silicon / Intel ZIPs passed native Mac CI (four desktop tests each); signatures are ad hoc, not Developer ID or notarized. Windows installer and Linux x64 packages are resource-verified; their installed desktop UI is not certified. Mac Docker EDA, full controller transistor timing, pads/ESD, noise/yield, INL/DNL/SINAD/ENOB and foundry approval remain separate.

Installers, native resource evidence and the bounded layout/SAR library are attached. Older failed iterations remain in the repository and originating worker.