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Fixes build break caused by halport commit. #631

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Merged
mozmck merged 1 commit into from
Aug 9, 2019
Merged

Fixes build break caused by halport commit. #631

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2 changes: 1 addition & 1 deletion src/hal/hal_lib.c
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Original file line number Diff line number Diff line change
Expand Up @@ -4157,7 +4157,7 @@ EXPORT_SYMBOL(hal_port_peek_commit);
EXPORT_SYMBOL(hal_port_write);
EXPORT_SYMBOL(hal_port_readable);
EXPORT_SYMBOL(hal_port_writable);
EXPORT_SYMBOL(hal_port_size);
EXPORT_SYMBOL(hal_port_buffer_size);
EXPORT_SYMBOL(hal_port_clear);

EXPORT_SYMBOL_GPL(hal_stream_create);
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143 changes: 0 additions & 143 deletions tests/pyhal/test
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Expand Up @@ -120,149 +120,6 @@ assert port_out.writable() == 0

assert port_in.read(8) == "12345678"

c.exit()
os.system("halrun -U")
exit(0)
from pyhal import *


c = component("hello")

port_in = c.pinNew("port-in", halType.PORT, pinDir.IN)
port_out = c.pinNew("port-out", halType.PORT, pinDir.OUT)

in_s = c.pinNew("in-s", halType.SIGNED, pinDir.IN)
out_s = c.pinNew("out-s", halType.SIGNED, pinDir.OUT)

in_u = c.pinNew("in-u", halType.UNSIGNED, pinDir.IN)
out_u = c.pinNew("out-u", halType.UNSIGNED, pinDir.OUT)

in_f = c.pinNew("in-f", halType.FLOAT, pinDir.IN)
out_f = c.pinNew("out-f", halType.FLOAT, pinDir.OUT)


in_io = c.pinNew("in-io", halType.BIT, pinDir.IO)
out_io = c.pinNew("out-io", halType.BIT, pinDir.IO)


c.makeReady()

import os



#test signed in/out pins
c.sigNew("testSig-S", halType.SIGNED)
c.sigLink("hello.in-s", "testSig-S")
c.sigLink("hello.out-s", "testSig-S")
out_s.value = -100
assert in_s.value == -100, "in_s.value should be -100. got {0}".format(in_s.value)
out_s.value = 34435
assert in_s.value == 34435, "in_s.value should be 34435. got {0}".format(in_s.value)


#test unsigned in/out pins
c.sigNew("testSig-U", halType.UNSIGNED)
c.sigLink("hello.in-u", "testSig-U")
c.sigLink("hello.out-u", "testSig-U")
out_u.value = 65535
assert in_u.value == out_u.value, "in_u.value should be {0}. got {0}".format(out_u.value, in_u.value)


#test float pins
c.sigNew("testSig-F", halType.FLOAT)
c.sigLink("hello.in-f", "testSig-F")
os.system("halcmd sets testSig-F -1000.0")

assert in_f.value == -1000.0
c.sigLink("hello.out-f", "testSig-F")

out_f.value = 333.333
assert in_f.value == 333.333

#test io bool
c.sigNew("testSig-IO", halType.BIT)
c.sigLink("hello.in-io", "testSig-IO")
c.sigLink("hello.out-io", "testSig-IO")

out_io.value = False
assert in_io.value == False
out_io.value = True
assert in_io.value == True

in_io.value = False
assert out_io.value == False



#now test hal port
c.sigNew("testSig-PORT", halType.PORT)
c.sigLink("hello.port-in", "testSig-PORT")
c.sigLink("hello.port-out", "testSig-PORT")

assert port_in.size() == 0
assert port_out.size() == 0

#make sure to allocate a port on the signal
os.system('halcmd sets testSig-PORT 9')

assert port_in.size() == 9
assert port_out.size() == 9


assert port_out.writable() == 8
assert port_in.readable() == 0


port_out.waitWritable(8)
assert port_out.write("hello")


assert port_in.readable() == 5
assert port_in.read(2) == "he"
assert port_in.peek(10) == ""
assert port_in.readable() == 3
assert port_in.read(3) == "llo"

assert port_in.readable() == 0
assert port_out.write("hello")
assert port_in.read(5) == "hello"

assert port_in.readable() == 0
assert port_in.read(5) == ''


assert port_out.writable() == 8


assert port_out.write("12345678") == 8

assert port_in.readable() == 8
assert port_out.writable() == 0

assert port_in.read(8) == "12345678"


assert port_out.write("12345678")
assert port_in.peek(4) == "1234"
assert port_in.readable() == 8
assert port_out.writable() == 0
assert port_in.peek_commit(4)
assert port_in.readable() == 4
assert port_out.writable() == 4
assert port_in.peek(4) == "5678"
assert port_in.peek(4) == "5678"
assert port_in.read() == "5678"
assert port_in.readable() == 0
assert port_out.writable() == 8


assert port_out.write("12345")
assert port_in.readable() == 5
assert port_in.clear()
assert port_in.readable() == 0


c.exit()
os.system("halrun -U")
exit(0)