Independent Watchdog Timer (IWDG)

Important to know is that the Independent Watchdog Timer (IWDG) is enabled by default, with a total countdown period from max to zero of 32 seconds.
The IWDG is used to detect and resolve any kind of malfunctions due to software failure. It triggers a reset when the watchdog counter reaches zero. It's clock uses the LSI, thus remaining active even if the main clock fails. It is up to the developer to implement a flow of feeding the watchdog timer (resetting the counter to its max value) at least once every 32 seconds. When using deepsleep modes, the IWDG counter can be frozen using the option bytes of the MCU.