2024.09

Mi-V Soft Processor platform      

• CoreTSE
  • Optional separate interrupt handlers for TX and RX.
  • Incorporate support for ECC error handling.
• CoreQSPI
  • First Release
• MIV_RV32_HAL
  • Fixed an issue where the MTVEC_BASE_ADDR_MASK macro was undefined when MIV_RV32_EXT_TIMER was defined.

Driver	Revision
CoreTSE	2.6.001
CoreQSPI	2.1.103