This project creates a counter in systemverilog and then uses that counter to create a custom AXI block. The custom block is then used in a block design to test it using systemVerilog test benches.
Most of the code was provided by the instructor for this lab. This was an introductory lab to creating custom IPs in Vivado and was meant to teach us how to create and use these custom blocks, and also how to test them using systemVerilog's powerful testing capabilities.