Gate diagram limitations

Gate diagram limitations

Quality of solutions
All gate diagrams generated by Logic Friday are checked against the truth table. However, it cannot be guaranteed that a generated gate diagram is the best possible solution to the problem.

Glitches and hazards
If you implement a Logic Friday gate diagram in hardware, you may see output glitches for some combinations of inputs. A glitch is a momentary transition to the wrong logic level at the output of a gate network. If a gate network has some interconnection of gates that could cause a glitch, it is said to have a hazard. In general, Logic Friday gate diagrams are not hazard free.

Whether glitches are important depends on the application. For example, if the network just drives an indicator LED glitches are unimportant. But if the network output is used to clock or clear a sequential logic device glitches may be very important.

A discussion of how to deal with hazards and glitches is beyond the scope of this help file. For further information, consult a logic design textbook.