This repository contains the project made for the "Reti Logiche" course at Politecnico di Milano for the academic year 2022/2023.
This project was carried out by my colleague, Riccardo Manfredonia, and myself.
The aim of the project was to create a small memory controller in VHDL to access some data and output it through four ports. The software used for this project was Xilinx Vivado.
You can read more about it in the report (written in Italian). Since there are some formatting issues with the MarkDown file, I also provided a PDF version.