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[None][opt] attn kernel epilogue fuse RopeQuant#14947

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NVIDIA:feat/deepseek_v4from
yunruis:user/yunruis/dsv4_attn_epilogue_fusion
Jul 7, 2026
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[None][opt] attn kernel epilogue fuse RopeQuant#14947
yunruis merged 3 commits into
NVIDIA:feat/deepseek_v4from
yunruis:user/yunruis/dsv4_attn_epilogue_fusion

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@yunruis yunruis commented Jun 4, 2026

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1. Summary

This PR integrates DeepSeek-V4 FMHA epilogue fusion into the TensorRT-LLM PyTorch MLA path.

Before this change, the DeepSeek-V4 attention path materialized the FMHA latent output and then launched a separate inverse-RoPE + FP8 quantization kernel before the DSv4 O projection BGEMM:

FMHA
  -> BF16 latent output
  -> standalone inverse-RoPE + E4M3 quant + FP32 scale
  -> DSv4 O projection BGEMM

With epilogue fusion enabled, trtllm-gen FMHA performs inverse RoPE and 1x128 E4M3 quantization in the FMHA correction epilogue, and directly writes the physical layout consumed by the DSv4 O projection BGEMM:

FMHA correction epilogue
  -> inverse RoPE
  -> 1x128 E4M3 quant + FP32 scale
  -> DSv4 O projection BGEMM

The optimization removes the standalone rope-quant kernel launch and avoids the intermediate latent write/read between FMHA and quantization. The O projection itself is not fused into FMHA; it still runs as the existing DSv4 FP8 BGEMM, now consuming (fp8_o, fp32_scale) produced by FMHA.

2. Applicable Scenarios

The feature is intentionally gated to the validated DeepSeek-V4 Pro configuration:

  • Model: DeepSeek-V4 Pro MLA / DSA path.
  • Parallelism: attention DP / DP-only attention heads, with local num_heads == num_heads_tp == 128.
  • GPU: SM100f path with matching trtllm-gen FMHA cubins.
  • Precision/layout: FP8 E4M3 Q/K/V/O path, FP8 KV cache, DSv4 O projection A in E4M3.
  • Attention mode: DeepSeek-V4 sparse MLA with paged KV.
  • Batch shape: context-only or generation-only batches. Mixed context + generation batches fall back because the fused output buffers currently do not carry an explicit token-offset contract for two FMHA calls writing one combined output.
  • Disabled cases: CP Helix, non-DSv4 models, non-FP8 KV cache, non-target DSv4 dimensions, missing sparse config, and user-disabled fusion.

The runtime kill switch is:

TRTLLM_DSV4_DISABLE_FMHA_EPILOGUE_FUSION=1

By default, the feature is allowed and the runtime gate decides whether the current batch can use the fused path.

3. Perf Gain

The kernel-level comparison should be reported as:

non_fused_total_us = standard_fmha_us + standalone_rope_quant_us
ep_fusion_fmha_us = FMHA time with DSv4 epilogue fusion enabled
speedup = non_fused_total_us / ep_fusion_fmha_us
saved_pct = 1 - ep_fusion_fmha_us / non_fused_total_us
sparse mode phase B Q KV standard_us rope_us baseline total fused_us speedup saved_pct
hca prefill 1 8192 8192 627.236 361.429 988.665 655.505 1.5082x 33.70%
hca prefill 4 8192 8192 2512.980 1488.042 4001.022 2540.840 1.5747x 36.50%
hca prefill 1 16384 16384 1216.700 736.190 1952.890 1278.080 1.5280x 34.55%
hca prefill 4 16384 16384 5044.020 3107.636 8151.656 5038.630 1.6178x 38.19%
csa prefill 1 8192 8192 1230.050 361.429 1591.479 1160.070 1.3719x 27.11%
csa prefill 4 8192 8192 5250.850 1488.042 6738.892 4925.850 1.3681x 26.90%
csa prefill 1 16384 16384 2815.160 736.190 3551.350 2642.630 1.3439x 25.59%
csa prefill 4 16384 16384 11646.100 3107.636 14753.736 10855.700 1.3591x 26.42%
hca generation 32 1 8192 9.340 2.690 12.030 10.528 1.1426x 12.48%
hca generation 32 4 8192 16.696 6.532 23.228 17.288 1.3436x 25.57%
csa generation 32 1 8192 19.683 2.690 22.373 17.142 1.3051x 23.38%
csa generation 32 4 8192 30.577 6.532 37.109 30.863 1.2024x 16.83%

4. Major Changes

4.1 New DSv4 Epilogue Fusion Inputs and Outputs

New runtime inputs/outputs are added for the fused path:

Field Direction Meaning
output / oPtr FMHA output E4M3 physical O buffer consumed by DSv4 O projection BGEMM
output_sf / oSfPtr FMHA output FP32 1x128 scale buffer for the E4M3 O buffer
dsv4_inv_rope_cos_sin_cache FMHA input FP32 inverse-RoPE cos/sin cache
enable_dsv4_epilogue_fusion runtime flag Enables DSv4 inverse-RoPE + FP8 quant in the FMHA epilogue
scaleBufM runtime scalar input Padded token stride derived from output_sf.size(2)

scaleBufM is an input scalar, not an output tensor. It describes the padded token stride of output_sf and is propagated to trtllm-gen so the kernel writes FP32 scales with the same layout allocated by TensorRT-LLM.

The fused output layout is:

fp8_o:
  dtype = E4M3
  shape = [num_groups, num_tokens, heads_per_group * v_head_dim]

output_sf:
  dtype = FP32
  shape = [num_groups, heads_per_group * (v_head_dim / 128), scaleBufM]

4.2 Python Model Forward Changes

The DeepSeek-V4 MLA forward path now has two possible attention outputs:

non-fused path:
  attn_output = BF16 latent
  _deepseek_v4_o_proj(attn_output, position_ids)
    -> standalone inverse-RoPE + FP8 quant
    -> DSv4 O projection BGEMM

fused path:
  dsv4_epilogue_output = (fp8_o, fp32_scale)
  _deepseek_v4_o_proj(dsv4_epilogue_output)
    -> DSv4 O projection BGEMM

The O projection call site remains unified in MLA.forward(). The fused path changes the input type to _deepseek_v4_o_proj() but does not move the O projection into FMHA.

For register_to_config, the MLA custom op contract is extended so custom-op execution can receive DSv4 fused buffers explicitly:

  • trtllm::create_mla_outputs creates the legacy output and, when the runtime gate passes, the DSv4 (fp8_o, output_sf) buffers.
  • trtllm::mla_custom_op_inplace accepts optional dsv4_output, dsv4_output_sf, and enable_dsv4_epilogue_fusion.
  • DeepSeek-V4 custom-op execution calls forward_impl_with_deepseek_v4(..., dsv4_epilogue_output=...).

This keeps the custom-op path functionally aligned with the eager Python path and avoids dropping the fused epilogue buffers before the O projection.

@yunruis yunruis changed the title User/yunruis/dsv4 attn epilogue fusion [None][opt] attn epilogue fuse RopeQuant Jun 4, 2026
@yunruis yunruis changed the title [None][opt] attn epilogue fuse RopeQuant [None][opt] attn kernel epilogue fuse RopeQuant Jun 4, 2026
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@yunruis yunruis marked this pull request as draft June 4, 2026 08:40
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@lfr-0531 lfr-0531 requested review from heyuhhh and mingyangHao June 4, 2026 08:49
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@yunruis yunruis marked this pull request as ready for review June 8, 2026 06:30
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@yunruis yunruis changed the title [None][opt] attn kernel epilogue fuse RopeQuant [None][opt] attn kernel epilogue fuse RopeQuant(Dont't Merge) Jun 10, 2026
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Comment thread tensorrt_llm/_torch/modules/attention.py
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@yunruis yunruis force-pushed the user/yunruis/dsv4_attn_epilogue_fusion branch from 2bd7d24 to d04b08e Compare July 6, 2026 08:32
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all comments has been resolved from my side. If you agree please mark it as resolved. Thanks @heyuhhh @mingyangHao

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All comments has been resolved.

@yunruis yunruis merged commit 344563d into NVIDIA:feat/deepseek_v4 Jul 7, 2026
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LFS objects already in storage (3240 files) — no sync needed.

These LFS-tracked files are already present in this repository's LFS storage:

  • cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/cubin/FmhaSm100aKernel_QE4m3KvE2m1OBfloat16H128PagedKvCausalP32VarSeqQ128Kv128PersistentContext.cubin.tar.zst
  • cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/cubin/FmhaSm100aKernel_QE4m3KvE2m1OBfloat16H128PagedKvCausalP32VarSeqQ128Kv128StaticContext.cubin.tar.zst
  • cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/cubin/FmhaSm100aKernel_QE4m3KvE2m1OBfloat16H128PagedKvCustomP32MultiCtasKvCgaVarSeqQ16Kv128StaticSwapsAbForGen.cubin.tar.zst
  • cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/cubin/FmhaSm100aKernel_QE4m3KvE2m1OBfloat16H128PagedKvCustomP32MultiCtasKvCgaVarSeqQ32Kv128StaticSwapsAbForGen.cubin.tar.zst
  • cpp/tensorrt_llm/kernels/trtllmGenKernels/fmha/cubin/FmhaSm100aKernel_QE4m3KvE2m1OBfloat16H128PagedKvCustomP32MultiCtasKvCgaVarSeqQ8Kv128StaticSwapsAbForGen.cubin.tar.zst
  • ...and 3235 more

yunruis added a commit to yunruis/TensorRT-LLM that referenced this pull request Jul 7, 2026
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yunruis added a commit to yunruis/TensorRT-LLM that referenced this pull request Jul 7, 2026
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