[None][fix] Exclude SM12x from bf16x2 FP8 cvt specialization in moe_a2a

[waynehacking8]

Description

Building main for consumer Blackwell (--cuda_architectures "120-real", CUDA 13.0) currently fails at ptxas:

ptxas .../moeAlltoAllKernels.ptx, line 49340; error : Unexpected instruction types specified for 'cvt'
ptxas .../moeAlltoAllKernels.ptx, line 49343; error : Unexpected instruction types specified for 'cvt'

Root cause: the BF16 -> FP8 vec_convert specialization from #11844 emits cvt.rn.satfinite.e4m3x2.bf16x2 behind __CUDA_ARCH__ >= 1000. sm_120/sm_121 (__CUDA_ARCH__ 1200/1210) pass that numeric check but don't have the bf16x2 source variant of this cvt, so ptxas rejects the TU and the whole 120-real/121-real build dies.

Fix: bound the specialization to the SM100 family (>= 1000 && < 1200). SM12x falls back to the generic float-path vec_convert directly above - the paired-cvt specialization is a pure optimization, and this is the quantized multi-device a2a path, so consumer single/dual-GPU setups don't exercise it in anger anyway.

Test Coverage

• Stock main with --cuda_architectures "120-real" on CUDA 13.0 reproduces the two ptxas errors above (RTX PRO 6000 host, bare-metal build_wheel.py --cpp_only).
• With this change the same build completes: moeAlltoAllKernels.cu.o compiles and libtensorrt_llm.so / libnvinfer_plugin_tensorrt_llm.so link (100%).
• No behavior change for SM100-family or pre-Blackwell architectures - the guard only narrows which arch gets the PTX fast path.

PR Checklist

• PR title follows the required format
• PR description explains the change
• Verified locally (build-level; the touched path is compile-time arch selection)

Summary by CodeRabbit

• Bug Fixes
  • Improved GPU architecture compatibility for certain mixed-precision conversions.
  • On newer SM 120/121 GPUs, the affected conversion now uses a safe fallback path instead of an unsupported instruction variant, preventing build issues.

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📥 Commits

Reviewing files that changed from the base of the PR and between e4aba85 and 113a838.

📒 Files selected for processing (1)

• cpp/tensorrt_llm/kernels/communicationKernels/moeAlltoAllKernels.cu

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📝 Walkthrough

Walkthrough

The compile-time CUDA architecture guard for the BF16→FP8 e4m3 paired-PTX vec_convert specialization in moeAlltoAllKernels.cu was narrowed to __CUDA_ARCH__ >= 1000 && __CUDA_ARCH__ < 1200, causing SM120/121 to use the generic float-path fallback.

Changes

Architecture Guard Fix

Layer / File(s)	Summary
Restrict paired-PTX vec_convert to SM100-SM119 cpp/tensorrt_llm/kernels/communicationKernels/moeAlltoAllKernels.cu	The __CUDA_ARCH__ guard on the BF16→FP8 e4m3 paired-PTX cvt.rn.satfinite.e4m3x2.bf16x2 specialization was changed from >= 1000 to >= 1000 && < 1200, with comments noting SM12x falls back to the generic implementation due to unsupported paired instructions.

Estimated code review effort: 1 (Trivial) | ~3 minutes

🚥 Pre-merge checks | ✅ 5

✅ Passed checks (5 passed)

Check name	Status	Explanation
Title check	✅ Passed	The title follows the required format and accurately summarizes the SM12x BF16x2 FP8 specialization fix.
Description check	✅ Passed	The description includes the required Description, Test Coverage, and PR Checklist sections with relevant details.
Docstring Coverage	✅ Passed	No functions found in the changed files to evaluate docstring coverage. Skipping docstring coverage check.
Linked Issues check	✅ Passed	Check skipped because no linked issues were found for this pull request.
Out of Scope Changes check	✅ Passed	Check skipped because no linked issues were found for this pull request.

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