[TRTLLM-14093][feat] Eagle3 support for MiniMax-M3 on the MSA backend#16021
[TRTLLM-14093][feat] Eagle3 support for MiniMax-M3 on the MSA backend#16021zheyuf wants to merge 2 commits into
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WalkthroughThis PR adds one-model Eagle3 speculative decoding support for MiniMax-M3. It updates the sparse KV cache manager's page-table and index handling, switches attention metadata to subclass ChangesMiniMax-M3 Eagle3 Speculative Decoding
Estimated code review effort: 4 (Complex) | ~60 minutes Sequence Diagram(s)sequenceDiagram
participant MiniMaxM3Model
participant MiniMaxM3DecoderLayer
participant SpecMetadata
participant TrtllmAttentionMetadata
MiniMaxM3Model->>MiniMaxM3DecoderLayer: forward(hidden_states, residual, spec_metadata)
MiniMaxM3DecoderLayer->>TrtllmAttentionMetadata: prepare() base KV lens/block offsets
TrtllmAttentionMetadata-->>MiniMaxM3DecoderLayer: prepared metadata
MiniMaxM3DecoderLayer->>SpecMetadata: maybe_capture_hidden_states(layer_idx, hidden_states, residual)
MiniMaxM3DecoderLayer-->>MiniMaxM3Model: hidden_states
Possibly related PRs
Suggested reviewers: 🚥 Pre-merge checks | ✅ 5✅ Passed checks (5 passed)
✨ Finishing Touches🧪 Generate unit tests (beta)
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⚠️ Outside diff range comments (1)
tensorrt_llm/_torch/pyexecutor/kv_cache_manager_v2.py (1)
2684-2737: 🩺 Stability & Availability | 🟠 Major | ⚡ Quick winTrack V1 draft registrations in the cleanup path
The V1 draft-manager branch never sets
draft_kv_cache, so a laterkv_cache.resize()failure skipsdraft_kv_cache_manager.free_resources(current_request)even though the request was already registered viaadd_sequence_batch. That leaves the dummy request behind and can break the next warmup/retry with the same request id.🤖 Prompt for AI Agents
Verify each finding against current code. Fix only still-valid issues, skip the rest with a brief reason, keep changes minimal, and validate. In `@tensorrt_llm/_torch/pyexecutor/kv_cache_manager_v2.py` around lines 2684 - 2737, The V1 draft-manager path in the request setup/cleanup flow does not register any handle for the draft allocation, so a later kv_cache.resize failure bypasses freeing the already-added dummy request. Update the cleanup logic around the draft_kv_cache_manager branch in the request preparation code to track that a V1 draft registration happened and call draft_kv_cache_manager.free_resources(current_request) on failure/retry paths, alongside the existing draft_kv_cache handling.
🧹 Nitpick comments (1)
tensorrt_llm/_torch/pyexecutor/kv_cache_manager_v2.py (1)
2686-2686: 📐 Maintainability & Code Quality | 🔵 Trivial | ⚡ Quick winPrefer
isinstanceoverhasattrduck-typing to distinguish manager type.
hasattr(draft_kv_cache_manager, "_create_kv_cache")distinguishes V2 vs V1-family managers via duck typing. Since this file definesKVCacheManagerV2itself,isinstance(draft_kv_cache_manager, KVCacheManagerV2)would be a more robust and idiomatic check.♻️ Proposed refactor
- if hasattr(draft_kv_cache_manager, "_create_kv_cache"): + if isinstance(draft_kv_cache_manager, KVCacheManagerV2):As per coding guidelines, "Prefer
isinstance()to duck typing where possible; use built-in exception types for error handling, not custom exceptions in most cases."🤖 Prompt for AI Agents
Verify each finding against current code. Fix only still-valid issues, skip the rest with a brief reason, keep changes minimal, and validate. In `@tensorrt_llm/_torch/pyexecutor/kv_cache_manager_v2.py` at line 2686, Replace the duck-typing check in KVCacheManagerV2 with an explicit type check: use isinstance(draft_kv_cache_manager, KVCacheManagerV2) instead of hasattr(..., "_create_kv_cache"). Update the manager-selection branch in KVCacheManagerV2 to rely on the concrete class name rather than probing for an internal method, keeping the existing behavior for V2 vs V1-family managers intact.Source: Coding guidelines
🤖 Prompt for all review comments with AI agents
Verify each finding against current code. Fix only still-valid issues, skip the
rest with a brief reason, keep changes minimal, and validate.
Outside diff comments:
In `@tensorrt_llm/_torch/pyexecutor/kv_cache_manager_v2.py`:
- Around line 2684-2737: The V1 draft-manager path in the request setup/cleanup
flow does not register any handle for the draft allocation, so a later
kv_cache.resize failure bypasses freeing the already-added dummy request. Update
the cleanup logic around the draft_kv_cache_manager branch in the request
preparation code to track that a V1 draft registration happened and call
draft_kv_cache_manager.free_resources(current_request) on failure/retry paths,
alongside the existing draft_kv_cache handling.
---
Nitpick comments:
In `@tensorrt_llm/_torch/pyexecutor/kv_cache_manager_v2.py`:
- Line 2686: Replace the duck-typing check in KVCacheManagerV2 with an explicit
type check: use isinstance(draft_kv_cache_manager, KVCacheManagerV2) instead of
hasattr(..., "_create_kv_cache"). Update the manager-selection branch in
KVCacheManagerV2 to rely on the concrete class name rather than probing for an
internal method, keeping the existing behavior for V2 vs V1-family managers
intact.
ℹ️ Review info
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📒 Files selected for processing (10)
tensorrt_llm/_torch/attention_backend/sparse/minimax_m3/cache_manager.pytensorrt_llm/_torch/attention_backend/sparse/minimax_m3/metadata.pytensorrt_llm/_torch/models/modeling_minimaxm3.pytensorrt_llm/_torch/pyexecutor/kv_cache_manager_v2.pytensorrt_llm/_torch/pyexecutor/model_engine.pytensorrt_llm/_torch/pyexecutor/py_executor_creator.pytensorrt_llm/runtime/kv_cache_manager_v2/_utils.pytests/integration/defs/accuracy/references/gsm8k.yamltests/integration/defs/accuracy/references/mmlu.yamltests/integration/defs/accuracy/test_llm_api_pytorch.py
… MiniMax-M3 Squashed port of feat/minimax-m3-eagle3 (PR NVIDIA#16021) onto feat/branch_m3. Target-side enablement for the Inferact/MiniMax-M3-EAGLE3 draft head on the reference (non-MSA) sparse backend: - Wire MiniMaxM3ForCausalLM as SpecDecOneEngineForCausalLM and capture Eagle3 aux hidden states at layer exit (fully TP-reduced; no cross-layer allreduce+norm fusion). - Rebase MiniMaxM3AttentionMetadata onto TrtllmAttentionMetadata (the shared per-step metadata is consumed by TRTLLM draft layers, the Eagle3 one-model worker, and engine isinstance gates; precedent: DSA and the M3 MSA metadata). - Route multi-token generation rows (spec verify: 1 + draft_len tokens) through the extend path; the decode branch stays reserved for batches where every row appends exactly one token. - Vectorized sync-free builder shared with a new on_update_kv_lens hook that re-derives seq_lens/prefix_lens/q_positions/out_cache_loc on device from the corrected kv_lens_cuda under overlap scheduler + spec (DSA pattern); in-bounds clamps cover the optimistic page-boundary overhang (max_seqlen_k SDPA width + slot gathers). - V1-family draft manager support in KVCacheManagerV2.add_dummy_requests (exception-safe); attention-DP dummy requests register in the draft manager; MiniMaxM3KVCacheManagerV2 opts out of shared draft layers under attention DP (its AttentionOp tensors are synthetic). - Creation-time guards: tree modes, disabled separate draft KV (disagg WAR), CUDA graphs, and MSA+spec (the in-builder MSA rejection is hoisted above routing so mixed batches cannot bypass it). - Accuracy test test_nvfp4_eagle3 (MMLU + GSM8K + acceptance probe, attention_dp parametrized) + reference rows. Signed-off-by: Zheyu Fu <zheyuf@NVIDIA.com> Validated on 4xB200 (NVFP4 tp4/ep4, draft_len=3, overlap scheduler on, eager) at this commit: - test_nvfp4_eagle3[attention_dp=False]: MMLU 85.50 / GSM8K 89.73 (refs 83/88), acceptance rate 0.709 / mean acceptance length 3.126 - test_nvfp4_eagle3[attention_dp=True]: MMLU 85.14 / GSM8K 91.32, acceptance rate 0.767 / mean acceptance length 3.302 - batch-1 greedy: 6.05 -> 17.05 tok/s (2.82x) - spec-off boot + generation clean (TRTLLM-Gen warmup now runs for M3 and is harmless) Signed-off-by: Zheyu Fu <zheyuf@NVIDIA.com>
… MiniMax-M3 Squashed port of feat/minimax-m3-eagle3 (PR NVIDIA#16021) onto feat/branch_m3. Target-side enablement for the Inferact/MiniMax-M3-EAGLE3 draft head on the reference (non-MSA) sparse backend: - Wire MiniMaxM3ForCausalLM as SpecDecOneEngineForCausalLM and capture Eagle3 aux hidden states at layer exit (fully TP-reduced; no cross-layer allreduce+norm fusion). - Rebase MiniMaxM3AttentionMetadata onto TrtllmAttentionMetadata (the shared per-step metadata is consumed by TRTLLM draft layers, the Eagle3 one-model worker, and engine isinstance gates; precedent: DSA and the M3 MSA metadata). - Route multi-token generation rows (spec verify: 1 + draft_len tokens) through the extend path; the decode branch stays reserved for batches where every row appends exactly one token. - Vectorized sync-free builder shared with a new on_update_kv_lens hook that re-derives seq_lens/prefix_lens/q_positions/out_cache_loc on device from the corrected kv_lens_cuda under overlap scheduler + spec (DSA pattern); in-bounds clamps cover the optimistic page-boundary overhang (max_seqlen_k SDPA width + slot gathers). - V1-family draft manager support in KVCacheManagerV2.add_dummy_requests (exception-safe); attention-DP dummy requests register in the draft manager; MiniMaxM3KVCacheManagerV2 opts out of shared draft layers under attention DP (its AttentionOp tensors are synthetic). - Creation-time guards: tree modes, disabled separate draft KV (disagg WAR), CUDA graphs, and MSA+spec (the in-builder MSA rejection is hoisted above routing so mixed batches cannot bypass it). - Accuracy test test_nvfp4_eagle3 (MMLU + GSM8K + acceptance probe, attention_dp parametrized) + reference rows. Validated on 4xB200 (NVFP4 tp4/ep4, draft_len=3, overlap scheduler on, eager) at this commit: - test_nvfp4_eagle3[attention_dp=False]: MMLU 85.50 / GSM8K 89.73 (refs 83/88), acceptance rate 0.709 / mean acceptance length 3.126 - test_nvfp4_eagle3[attention_dp=True]: MMLU 85.14 / GSM8K 91.32, acceptance rate 0.767 / mean acceptance length 3.302 - batch-1 greedy: 6.05 -> 17.05 tok/s (2.82x) - spec-off boot + generation clean (TRTLLM-Gen warmup now runs for M3 and is harmless) Signed-off-by: Zheyu Fu <zheyuf@NVIDIA.com>
… MiniMax-M3 Squashed port of feat/minimax-m3-eagle3 (PR NVIDIA#16021) onto feat/branch_m3. Target-side enablement for the Inferact/MiniMax-M3-EAGLE3 draft head on the reference (non-MSA) sparse backend: - Wire MiniMaxM3ForCausalLM as SpecDecOneEngineForCausalLM and capture Eagle3 aux hidden states at layer exit (fully TP-reduced; no cross-layer allreduce+norm fusion). - Rebase MiniMaxM3AttentionMetadata onto TrtllmAttentionMetadata (the shared per-step metadata is consumed by TRTLLM draft layers, the Eagle3 one-model worker, and engine isinstance gates; precedent: DSA and the M3 MSA metadata). - Route multi-token generation rows (spec verify: 1 + draft_len tokens) through the extend path; the decode branch stays reserved for batches where every row appends exactly one token. - Vectorized sync-free builder shared with a new on_update_kv_lens hook that re-derives seq_lens/prefix_lens/q_positions/out_cache_loc on device from the corrected kv_lens_cuda under overlap scheduler + spec (DSA pattern); in-bounds clamps cover the optimistic page-boundary overhang (max_seqlen_k SDPA width + slot gathers). - V1-family draft manager support in KVCacheManagerV2.add_dummy_requests (exception-safe); attention-DP dummy requests register in the draft manager; MiniMaxM3KVCacheManagerV2 opts out of shared draft layers under attention DP (its AttentionOp tensors are synthetic). - Creation-time guards: tree modes, disabled separate draft KV (disagg WAR), CUDA graphs, and MSA+spec (the in-builder MSA rejection is hoisted above routing so mixed batches cannot bypass it). - Accuracy test test_nvfp4_eagle3 (MMLU + GSM8K + acceptance probe, attention_dp parametrized) + reference rows. Validated on 4xB200 (NVFP4 tp4/ep4, draft_len=3, overlap scheduler on, eager) at this commit: - test_nvfp4_eagle3[attention_dp=False]: MMLU 85.50 / GSM8K 89.73 (refs 83/88), acceptance rate 0.709 / mean acceptance length 3.126 - test_nvfp4_eagle3[attention_dp=True]: MMLU 85.14 / GSM8K 91.32, acceptance rate 0.767 / mean acceptance length 3.302 - batch-1 greedy: 6.05 -> 17.05 tok/s (2.82x) - spec-off boot + generation clean (TRTLLM-Gen warmup now runs for M3 and is harmless) Signed-off-by: Zheyu Fu <zheyuf@NVIDIA.com>
… MiniMax-M3 Squashed port of feat/minimax-m3-eagle3 (PR NVIDIA#16021) onto feat/branch_m3. Target-side enablement for the Inferact/MiniMax-M3-EAGLE3 draft head on the reference (non-MSA) sparse backend: - Wire MiniMaxM3ForCausalLM as SpecDecOneEngineForCausalLM and capture Eagle3 aux hidden states at layer exit (fully TP-reduced; no cross-layer allreduce+norm fusion). - Rebase MiniMaxM3AttentionMetadata onto TrtllmAttentionMetadata (the shared per-step metadata is consumed by TRTLLM draft layers, the Eagle3 one-model worker, and engine isinstance gates; precedent: DSA and the M3 MSA metadata). - Route multi-token generation rows (spec verify: 1 + draft_len tokens) through the extend path; the decode branch stays reserved for batches where every row appends exactly one token. - Vectorized sync-free builder shared with a new on_update_kv_lens hook that re-derives seq_lens/prefix_lens/q_positions/out_cache_loc on device from the corrected kv_lens_cuda under overlap scheduler + spec (DSA pattern); in-bounds clamps cover the optimistic page-boundary overhang (max_seqlen_k SDPA width + slot gathers). - V1-family draft manager support in KVCacheManagerV2.add_dummy_requests (exception-safe); attention-DP dummy requests register in the draft manager; MiniMaxM3KVCacheManagerV2 opts out of shared draft layers under attention DP (its AttentionOp tensors are synthetic). - Creation-time guards: tree modes, disabled separate draft KV (disagg WAR), CUDA graphs, and MSA+spec (the in-builder MSA rejection is hoisted above routing so mixed batches cannot bypass it). - Accuracy test test_nvfp4_eagle3 (MMLU + GSM8K + acceptance probe, attention_dp parametrized) + reference rows. Validated on 4xB200 (NVFP4 tp4/ep4, draft_len=3, overlap scheduler on, eager) at this commit: - test_nvfp4_eagle3[attention_dp=False]: MMLU 85.50 / GSM8K 89.73 (refs 83/88), acceptance rate 0.709 / mean acceptance length 3.126 - test_nvfp4_eagle3[attention_dp=True]: MMLU 85.14 / GSM8K 91.32, acceptance rate 0.767 / mean acceptance length 3.302 - batch-1 greedy: 6.05 -> 17.05 tok/s (2.82x) - spec-off boot + generation clean (TRTLLM-Gen warmup now runs for M3 and is harmless) Signed-off-by: Zheyu Fu <zheyuf@NVIDIA.com>
… MiniMax-M3 Squashed port of feat/minimax-m3-eagle3 (PR NVIDIA#16021) onto feat/branch_m3. Target-side enablement for the Inferact/MiniMax-M3-EAGLE3 draft head on the reference (non-MSA) sparse backend: - Wire MiniMaxM3ForCausalLM as SpecDecOneEngineForCausalLM and capture Eagle3 aux hidden states at layer exit (fully TP-reduced; no cross-layer allreduce+norm fusion). - Rebase MiniMaxM3AttentionMetadata onto TrtllmAttentionMetadata (the shared per-step metadata is consumed by TRTLLM draft layers, the Eagle3 one-model worker, and engine isinstance gates; precedent: DSA and the M3 MSA metadata). - Route multi-token generation rows (spec verify: 1 + draft_len tokens) through the extend path; the decode branch stays reserved for batches where every row appends exactly one token. - Vectorized sync-free builder shared with a new on_update_kv_lens hook that re-derives seq_lens/prefix_lens/q_positions/out_cache_loc on device from the corrected kv_lens_cuda under overlap scheduler + spec (DSA pattern); in-bounds clamps cover the optimistic page-boundary overhang (max_seqlen_k SDPA width + slot gathers). - V1-family draft manager support in KVCacheManagerV2.add_dummy_requests (exception-safe); attention-DP dummy requests register in the draft manager; MiniMaxM3KVCacheManagerV2 opts out of shared draft layers under attention DP (its AttentionOp tensors are synthetic). - Creation-time guards: tree modes, disabled separate draft KV (disagg WAR), CUDA graphs, and MSA+spec (the in-builder MSA rejection is hoisted above routing so mixed batches cannot bypass it). - Accuracy test test_nvfp4_eagle3 (MMLU + GSM8K + acceptance probe, attention_dp parametrized) + reference rows. Validated on 4xB200 (NVFP4 tp4/ep4, draft_len=3, overlap scheduler on, eager) at this commit: - test_nvfp4_eagle3[attention_dp=False]: MMLU 85.50 / GSM8K 89.73 (refs 83/88), acceptance rate 0.709 / mean acceptance length 3.126 - test_nvfp4_eagle3[attention_dp=True]: MMLU 85.14 / GSM8K 91.32, acceptance rate 0.767 / mean acceptance length 3.302 - batch-1 greedy: 6.05 -> 17.05 tok/s (2.82x) - spec-off boot + generation clean (TRTLLM-Gen warmup now runs for M3 and is harmless) Signed-off-by: Zheyu Fu <zheyuf@NVIDIA.com>
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… MiniMax-M3 Squashed port of feat/minimax-m3-eagle3 (PR NVIDIA#16021) onto feat/branch_m3. Target-side enablement for the Inferact/MiniMax-M3-EAGLE3 draft head on the reference (non-MSA) sparse backend: - Wire MiniMaxM3ForCausalLM as SpecDecOneEngineForCausalLM and capture Eagle3 aux hidden states at layer exit (fully TP-reduced; no cross-layer allreduce+norm fusion). - Rebase MiniMaxM3AttentionMetadata onto TrtllmAttentionMetadata (the shared per-step metadata is consumed by TRTLLM draft layers, the Eagle3 one-model worker, and engine isinstance gates; precedent: DSA and the M3 MSA metadata). - Route multi-token generation rows (spec verify: 1 + draft_len tokens) through the extend path; the decode branch stays reserved for batches where every row appends exactly one token. - Vectorized sync-free builder shared with a new on_update_kv_lens hook that re-derives seq_lens/prefix_lens/q_positions/out_cache_loc on device from the corrected kv_lens_cuda under overlap scheduler + spec (DSA pattern); in-bounds clamps cover the optimistic page-boundary overhang (max_seqlen_k SDPA width + slot gathers). - V1-family draft manager support in KVCacheManagerV2.add_dummy_requests (exception-safe); attention-DP dummy requests register in the draft manager; MiniMaxM3KVCacheManagerV2 opts out of shared draft layers under attention DP (its AttentionOp tensors are synthetic). - Creation-time guards: tree modes, disabled separate draft KV (disagg WAR), CUDA graphs, and MSA+spec (the in-builder MSA rejection is hoisted above routing so mixed batches cannot bypass it). - Accuracy test test_nvfp4_eagle3 (MMLU + GSM8K + acceptance probe, attention_dp parametrized) + reference rows. Validated on 4xB200 (NVFP4 tp4/ep4, draft_len=3, overlap scheduler on, eager) at this commit: - test_nvfp4_eagle3[attention_dp=False]: MMLU 85.50 / GSM8K 89.73 (refs 83/88), acceptance rate 0.709 / mean acceptance length 3.126 - test_nvfp4_eagle3[attention_dp=True]: MMLU 85.14 / GSM8K 91.32, acceptance rate 0.767 / mean acceptance length 3.302 - batch-1 greedy: 6.05 -> 17.05 tok/s (2.82x) - spec-off boot + generation clean (TRTLLM-Gen warmup now runs for M3 and is harmless) Signed-off-by: Zheyu Fu <zheyuf@NVIDIA.com> (cherry picked from commit 448c489) Signed-off-by: Zheyu Fu <zheyuf@nvidia.com>
… MiniMax-M3 Squashed port of feat/minimax-m3-eagle3 (PR NVIDIA#16021) onto feat/branch_m3. Target-side enablement for the Inferact/MiniMax-M3-EAGLE3 draft head on the reference (non-MSA) sparse backend: - Wire MiniMaxM3ForCausalLM as SpecDecOneEngineForCausalLM and capture Eagle3 aux hidden states at layer exit (fully TP-reduced; no cross-layer allreduce+norm fusion). - Rebase MiniMaxM3AttentionMetadata onto TrtllmAttentionMetadata (the shared per-step metadata is consumed by TRTLLM draft layers, the Eagle3 one-model worker, and engine isinstance gates; precedent: DSA and the M3 MSA metadata). - Route multi-token generation rows (spec verify: 1 + draft_len tokens) through the extend path; the decode branch stays reserved for batches where every row appends exactly one token. - Vectorized sync-free builder shared with a new on_update_kv_lens hook that re-derives seq_lens/prefix_lens/q_positions/out_cache_loc on device from the corrected kv_lens_cuda under overlap scheduler + spec (DSA pattern); in-bounds clamps cover the optimistic page-boundary overhang (max_seqlen_k SDPA width + slot gathers). - V1-family draft manager support in KVCacheManagerV2.add_dummy_requests (exception-safe); attention-DP dummy requests register in the draft manager; MiniMaxM3KVCacheManagerV2 opts out of shared draft layers under attention DP (its AttentionOp tensors are synthetic). - Creation-time guards: tree modes, disabled separate draft KV (disagg WAR), CUDA graphs, and MSA+spec (the in-builder MSA rejection is hoisted above routing so mixed batches cannot bypass it). - Accuracy test test_nvfp4_eagle3 (MMLU + GSM8K + acceptance probe, attention_dp parametrized) + reference rows. Validated on 4xB200 (NVFP4 tp4/ep4, draft_len=3, overlap scheduler on, eager) at this commit: - test_nvfp4_eagle3[attention_dp=False]: MMLU 85.50 / GSM8K 89.73 (refs 83/88), acceptance rate 0.709 / mean acceptance length 3.126 - test_nvfp4_eagle3[attention_dp=True]: MMLU 85.14 / GSM8K 91.32, acceptance rate 0.767 / mean acceptance length 3.302 - batch-1 greedy: 6.05 -> 17.05 tok/s (2.82x) - spec-off boot + generation clean (TRTLLM-Gen warmup now runs for M3 and is harmless) Signed-off-by: Zheyu Fu <zheyuf@NVIDIA.com> (cherry picked from commit 448c489) Signed-off-by: Zheyu Fu <zheyuf@nvidia.com>
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…x-M3 on the MSA backend Port of brb-nv#4 (head 499a369) onto main. - Enable one-model Eagle3 for MiniMax-M3: spec-metadata capture hooks in the decoder layers, SpecDecOneEngineForCausalLM base, and a separate draft KV cache manager (the MSA manager's INDEX_KEY-coalesced pools expose synthetic AttentionOp tensors dense draft layers cannot share, so it opts out of shared draft layers even under attention DP). - Default the one-model draft KV manager to V2 under V2 targets, with a draft page-size capability (the draft manager runs at tokens_per_block=32 to avoid a trtllm-gen IMA at 128 on the drafter's generation kernels; the MSA target requires 128). - MSA multi-token decode for spec verify: per-token plan rows, causal ladder masks in the dense SDPA path, and proxy scratch sized by the worst-case decode token count instead of the batch size. - CUDA graphs + overlap scheduler support: graph-safe max_k baking, an on_update_kv_lens hook that re-derives MSA slots/bounds on device from the corrected kv_lens, and kv_lens_cuda save/restore during graph warmup. Conflicts against main's revised MSA backend (NVIDIA#16291) were resolved by keeping main's _build_decode_plans naming and per-layer eager planning; the side branch's eager-plan dedup and HND index-K tests never landed on main and are not resurrected here. Signed-off-by: Zheyu Fu <zheyuf@NVIDIA.com>
…orker spec-dec prep The Eagle3 one-model change in this PR widened Eagle3OneModelWorker._prepare_attn_metadata_for_spec_dec to take an extra spec_metadata argument (for CUDA-graph-safe kv_lens_cuda save/restore). MTPEagleDynamicTreeWorker (via MTPEagleWorker) inherits that base but keeps its own single-arg override whose body calls super() with only attn_metadata, so the dynamic-tree MTP path raises TypeError: missing 1 required positional argument 'spec_metadata' at runtime. Thread spec_metadata through the override, its super() call, and the call site to match the base signature. Signed-off-by: Zheyu Fu <zheyuf@NVIDIA.com>
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[by Codex] @liji-nv Could you please review this PR? Thank you! |
Overview
Adds one-model Eagle3 speculative decoding for MiniMax-M3 on the MSA
backend, with overlap scheduler and CUDA graph support.
This PR is for InferenceX Minimax-M3 bringup and is previous merged in side branch: brb-nv#4
What this enables
decoder layers,
SpecDecOneEngineForCausalLMbase, and a separate draft KVcache manager. The MSA manager coalesces an index-K pool into its KV pages
and exposes only synthetic
AttentionOptensors, which the dense Eagle3drafter cannot attend against — so it opts out of shared draft layers
(
supports_shared_draft_layers = False) and requires the separate draftmanager even under attention DP.
capability: the separate draft manager runs at
tokens_per_block=32to avoida trtllm-gen IMA at 128 on the drafter's generation kernels, while the MSA
target requires 128 (
draft_manager_tokens_per_block).masks in the dense SDPA path, and proxy scratch sized by the worst-case decode
token count instead of the batch size.
max_kbaking, anon_update_kv_lenshook that re-derives MSA slots/bounds on device from thecorrected
kv_lens, andkv_lens_cudasave/restore during graph warmup.Validation
All numbers below are from the source PR's runs (4×B200, TP4/EP4, Eagle3
draft_len=3, out-of-the-box config, no env vars). CI on this ported branch ispending (
/bot run).Accuracy & acceptance —
test_nvfp4_eagle3(MSA + CUDA graphs + overlap scheduler)Non-spec references: MMLU 85.11 / GSM8K 91.32 — accuracy-neutral.
Acceptance rate reference: 0.839 / 3.518 on vLLM https://huggingface.co/Inferact/MiniMax-M3-EAGLE3
Known issues (base-branch, not addressed here)
tokens_per_block=128: the drafter's trtllm-gengeneration kernels hit an illegal memory access at page 128, independent of
MSA. Worked around via the draft manager's page-size capability (draft runs at
32); needs a kernel-team fix, after which the attribute can be removed.
total_q × num_qo_heads ≤ 65536boundsEagle3 (4 verify tokens) at max_batch_size 1024 with TP4-sharded heads and 256
under attention DP; the test caps accordingly.
Test plan
/bot run— builds the branch and runs the MSA+Eagle3 accuracy tests(
test_nvfp4_eagle3, added tollm_function_core.txt).