[https://nvbugs/6422343][fix] Retain the CPU source tensor as self._flash_mla_src_block_ids_cpu on the…#16071
[https://nvbugs/6422343][fix] Retain the CPU source tensor as self._flash_mla_src_block_ids_cpu on the…#16071trtllm-agent wants to merge 2 commits into
self._flash_mla_src_block_ids_cpu on the…#16071Conversation
📝 WalkthroughWalkthroughModifies ChangesFlashMLA Metadata Fix and Test Waiver Cleanup
Estimated code review effort: 2 (Simple) | ~10 minutes Possibly related PRs
Suggested reviewers: 🚥 Pre-merge checks | ✅ 5✅ Passed checks (5 passed)
✨ Finishing Touches🧪 Generate unit tests (beta)
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🧹 Nitpick comments (1)
tensorrt_llm/_torch/attention_backend/trtllm.py (1)
690-690: 📐 Maintainability & Code Quality | 🔵 Trivial | ⚡ Quick winDeclare
_flash_mla_src_block_ids_cpuas a typed dataclass field for consistency.Sibling private state on this dataclass (e.g.
_flash_mla_metadata_valid) is declared viafield(default=..., init=False, repr=False)with a type annotation._flash_mla_src_block_ids_cpuis instead created ad hoc via plain attribute assignment, which is inconsistent with the class's own convention and less friendly to static type checkers.♻️ Suggested fix
_flash_mla_metadata_valid: bool = field(default=False, init=False, repr=False) + # Retains the pinned CPU source tensor for the FlashMLA H2D copies so it + # outlives async, non-blocking copies issued during CUDA-graph capture. + _flash_mla_src_block_ids_cpu: Optional[torch.Tensor] = field( + default=None, init=False, repr=False)As per coding guidelines, "Annotate class members and variables when necessary, especially for dataclasses and NamedTuple."
🤖 Prompt for AI Agents
Verify each finding against current code. Fix only still-valid issues, skip the rest with a brief reason, keep changes minimal, and validate. In `@tensorrt_llm/_torch/attention_backend/trtllm.py` at line 690, Declare `_flash_mla_src_block_ids_cpu` as an explicit typed dataclass field on the class instead of creating it ad hoc in the `trtllm.py` attention backend. Update the dataclass definition for `TRTLLM`/the owning class to include a type annotation and a `field(default=..., init=False, repr=False)` entry, matching the existing convention used by `_flash_mla_metadata_valid` and related private state. Then remove the plain assignment in the initialization path and rely on the declared field so the member is consistent and static type checkers can see it.Source: Coding guidelines
🤖 Prompt for all review comments with AI agents
Verify each finding against current code. Fix only still-valid issues, skip the
rest with a brief reason, keep changes minimal, and validate.
Nitpick comments:
In `@tensorrt_llm/_torch/attention_backend/trtllm.py`:
- Line 690: Declare `_flash_mla_src_block_ids_cpu` as an explicit typed
dataclass field on the class instead of creating it ad hoc in the `trtllm.py`
attention backend. Update the dataclass definition for `TRTLLM`/the owning class
to include a type annotation and a `field(default=..., init=False, repr=False)`
entry, matching the existing convention used by `_flash_mla_metadata_valid` and
related private state. Then remove the plain assignment in the initialization
path and rely on the declared field so the member is consistent and static type
checkers can see it.
ℹ️ Review info
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📒 Files selected for processing (2)
tensorrt_llm/_torch/attention_backend/trtllm.pytests/integration/test_lists/waives.txt
💤 Files with no reviewable changes (1)
- tests/integration/test_lists/waives.txt
…pletes prepare_flash_mla uses non_blocking=True copies from a locally-scoped pinned CPU tensor. Under heavy warmup (MTP+ADP+cuda_graph+torch_compile+chunked_prefill), the tensor can be reclaimed by Python before the DMA finishes, leaving stale/garbage entries in the device block-ID buffers and later producing an illegal memory access from the FlashMLA kernel. Pin the source buffer to the metadata object so its lifetime spans the async copy. Signed-off-by: trtllm-agent <296075020+trtllm-agent@users.noreply.github.com>
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Summary
self._flash_mla_src_block_ids_cpuon the metadata object so its lifetime spans the async DMA. Also removed the H20 waivers for this bug.Test plan
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Bug Fixes
Tests