v1.1.0-agc — AERIS-10 Hybrid AGC + FPGA Timing Hardening

AERIS-10 Hybrid AGC System + FPGA Timing Hardening

Full hybrid AGC implementation spanning FPGA, STM32, and GUI layers with FPGA timing margin improvements and two rounds of multi-agent code review fixes (20 bugs total).

Timing

Metric	Value	Previous (v1.0.0)
WNS	+0.080 ns	+0.088 ns
WNS (400MHz)	+0.339 ns	+0.002 ns
WHS	+0.056 ns	+0.059 ns
WPWS	+0.361 ns	+0.361 ns
Failing Endpoints	0	0
All constraints met	Yes	Yes

Utilization (xc7a50tftg256-2)

Resource	Used	Available	Util%
LUTs	10,252	32,600	31.4%
Flip-Flops	12,820	65,200	19.7%
BRAM	17.5	75	23.3%
DSP48E1	112	120	93.3%
IOB	82	170	48.2%

What Changed (from v1.0.0-ft2232h)

Hybrid AGC System (Phases 1–7)

• FPGA inner loop: rx_gain_control.v — per-sample gain adjustment with saturation tracking, signed gain range -7 to +7
• FPGA registers: 0x28–0x2C (enable, target, attack, decay, holdoff) with status readback via status_words[4]
• STM32 outer loop: AgcOuterLoop class — per-frame ADAR1000 VGA common gain (0–31 dB, 0.5 dB steps) based on FPGA saturation metrics via DIG_5 GPIO
• STM32 integration: AGC register forwarding, status polling, GUI command routing in main.cpp
• GUI controls: AGC enable/disable, parameter tuning, status readback in both tkinter and PyQt6 dashboards
• GUI visualization: Real-time AGC gain/peak/saturation plotting widget with 500ms redraw throttle

FPGA Timing Hardening (400MHz WNS: +0.002 ns → +0.339 ns)

• DONT_TOUCH on output BUFG in adc_clk_mmcm.v to prevent AggressiveExplore cascade replication
• NCO→mixer fabric pipeline registers in ddc_400m.v break critical 1.5 ns route
• Clock uncertainty reduced 200 ps → 100 ps in adc_clk_mmcm.xdc
• Updated golden/cosim references for +1 cycle pipeline latency

Bug Fixes (20 total across two code review rounds)

• STM32: uint32_t underflow guard in processStartFlag, snprintf buffer safety in getSystemStatusForGUI, early-return error masking in checkSystemHealth, emergency blink delay
• GUI: opcode set conflict (0x03), V7 diagnostics error count wiring, replay mode label fix, Python 3.12 GIL crash fix
• FPGA: sign-extension in rx_gain_control.v, FT601 signal comment corrections, self-test timeout comment
• CI: test_v7.py added to pytest command, ruff lint clean

Test Suite

Layer	Tests	Status
Python (GUI)	120 (82 tkinter + 38 PyQt6)	Pass
MCU (C/C++)	21 (20 C + 1 C++ w/ 13 AGC sub-tests)	Pass
FPGA (iverilog)	25 (incl. 68 RX gain control checks)	Pass
Cross-layer	29	Pass
Total	195	All pass

Assets

• radar_system_top_50t.bit — Production bitstream (program via Vivado/xsdb)
• 02_timing_summary.rpt — Post-route timing report
• 04_utilization.rpt — Post-route utilization report

Build Environment

• Vivado 2025.2 (lin64)
• Device: xc7a50tftg256-2 (speed grade -2, PRODUCTION)
• Top module: radar_system_top_50t
• Build directives: ExtraNetDelay_high place, 3x AggressiveExplore phys_opt