AFU written in VHDL

[marcomontini]

Hi,
I am studying OPAE with BBB from examples available here https://github.com/OPAE/intel-fpga-bbb/tree/master/samples/tutorial. According to these examples I can see that CCI-P protocol between the FIU and the AFU is written in System Verilog. So I have two questions; at first, if I had an accelerator written in VHDL is it possible to interface it with CCI-P protocol? Or is it necessary that the AFU is written in SV? Then, I have seen the simple example "01_hello_world" and I have studied the file "cci_hello_afu.sv"; so, if I had an independent module (in VHDL or System Verilog) how could I configure it with the CCI-P protocol? It is not very clear to me this passage because of the example "Hello World" is too simple.

Thank you

Marco Montini

[michael-adler]

You can certainly include VHDL modules along with System Verilog (SV). However, you will probably find the CCI-P data structure definitions difficult to port. Most projects using VHDL implement the basic CCI-P requirements in SV and then construct their own interfaces to the VHDL code.

[marcomontini]

Ok but I do not understand very clear how to use a VHDL accelerator with cci-p protocol in SV. How should I modify the ccip_std_afu file to match with my accelerator if they are written in two different HDL languages? Are there some examples? Thanks for your help Il mercoledì 21 marzo 2018, Michael Adler <notifications@github.com> ha scritto:

…

You can certainly include VHDL modules along with System Verilog (SV). However, you will probably find the CCI-P data structure definitions difficult to port. Most projects using VHDL implement the basic CCI-P requirements in SV and then construct their own interfaces to the VHDL code. — You are receiving this because you authored the thread. Reply to this email directly, view it on GitHub <#15 (comment)>, or mute the thread <https://github.com/notifications/unsubscribe-auth/Af0197ksm8x1mUSLe7r7-OUlN3JsohsLks5tgpnCgaJpZM4S1A-4> .

[michael-adler]

Quartus and most RTL simulators support module/port instantiation across Verilog and VHDL.

I'm not suggesting you send CCI-P to VHDL. I'm suggesting you write the CCI-P portion in SystemVerilog and, if you want to use VHDL for the rest of your design, use either an application-specific protocol or some standard (e.g. Avalon) for the transition to VHDL.

[marcomontini]

I am using Quartus Prime 17.0 because of I downloaded it together with Intel OpenCL SDK for FPGA. I tried to realize a module instantiation but I have some errors including: "module instantiations in compilation scope are not allowed 16960". Is it possible that Quartus Prime does not support the instantiations across Verilog and VHDL? Even though Quartus II supports them? Thanks for your help 2018-03-22 1:05 GMT+01:00 Michael Adler <notifications@github.com>:

…

Quartus and most RTL simulators support module/port instantiation across Verilog and VHDL. I'm not suggesting you send CCI-P to VHDL. I'm suggesting you write the CCI-P portion in SystemVerilog and, if you want to use VHDL for the rest of your design, use either an application-specific protocol or some standard (e.g. Avalon) for the transition to VHDL. — You are receiving this because you authored the thread. Reply to this email directly, view it on GitHub <#15 (comment)>, or mute the thread <https://github.com/notifications/unsubscribe-auth/Af0196V1Est0w0ijrA6IXpH9xL9-e2Npks5tguregaJpZM4S1A-4> .

[marcomontini]

I solved the problem by using a different syntax and now the instantiation is correct. Thanks again for your support. ᐧ <http://www.avg.com/email-signature?utm_medium=email&utm_source=link&utm_campaign=sig-email&utm_content=webmail> Mail priva di virus. www.avg.com <http://www.avg.com/email-signature?utm_medium=email&utm_source=link&utm_campaign=sig-email&utm_content=webmail> <#DAB4FAD8-2DD7-40BB-A1B8-4E2AA1F9FDF2> 2018-03-22 12:53 GMT+01:00 Marco Montini <marcomontini4@gmail.com>:

…

I am using Quartus Prime 17.0 because of I downloaded it together with Intel OpenCL SDK for FPGA. I tried to realize a module instantiation but I have some errors including: "module instantiations in compilation scope are not allowed 16960". Is it possible that Quartus Prime does not support the instantiations across Verilog and VHDL? Even though Quartus II supports them? Thanks for your help 2018-03-22 1:05 GMT+01:00 Michael Adler ***@***.***>: > Quartus and most RTL simulators support module/port instantiation across > Verilog and VHDL. > > I'm not suggesting you send CCI-P to VHDL. I'm suggesting you write the > CCI-P portion in SystemVerilog and, if you want to use VHDL for the rest of > your design, use either an application-specific protocol or some standard > (e.g. Avalon) for the transition to VHDL. > > — > You are receiving this because you authored the thread. > Reply to this email directly, view it on GitHub > <#15 (comment)>, > or mute the thread > <https://github.com/notifications/unsubscribe-auth/Af0196V1Est0w0ijrA6IXpH9xL9-e2Npks5tguregaJpZM4S1A-4> > . >