OpenCoreLabsX contributor call: RTL and verification tasks

[briann-bui]

OpenCoreLabsX contributor call

We are building reusable, well-verified SystemVerilog IP for FPGA and ASIC projects. Contributors interested in RTL design, UVM, assertions, coverage, documentation, or technical review are welcome.

Open work

Difficulty	Area	Issue	Good fit for
Beginner-friendly	Timer / PWM DV	Boundary-condition regression	A focused UVM test, assertion set, or coverage group
Intermediate	I2C DV	I2C slave BFM and corner cases	Protocol BFM, scoreboard, ACK/NACK tests
Intermediate	USART DV	Serial monitor and error injection	Serial decoding, RX stimulus, error tests
Advanced	QSPI / AXI DV	Flash model and end-to-end XIP regression	QSPI modeling, AXI backpressure, scoreboarding
New IP	RTL + DV	Reusable APB GPIO controller proposal	Specification, RTL, UVM, assertions, docs

How to join

1. Read our contribution rules.
2. Open the issue that interests you and comment with the part you want to own.
3. Wait for scope agreement before a large or interface-changing implementation.
4. Fork the target repository, create a focused branch, and open a pull request linked to the issue.

You do not need to implement an entire issue alone. Small, reviewable contributions are encouraged. Maintainers can help split an issue into a first task.

Review standard

Behavioral changes need deterministic self-checking tests. RTL changes must include matching documentation and verification. Pull requests should report the exact lint and simulation commands used.

Questions are welcome in this issue. Tell us your RTL/DV experience and what kind of task you want, and we will suggest a starting point.