v11.0.4

What's Changed

• Chore: Update crate versions to 11.0.4 @[patina-automation[bot]](https://github.com/apps/patina-automation) (#197)
  
  Change Details

    An automatically created pull request to update the version of the repo due to a release.

  ---

• Fix multiple AArch64 bugs @cfernald (#195)
  
  Change Details

    ## Description

  This commit fixes two bugs in the aarch64 implementation.

  1. The cache operations routine is incrementing by the mask instead of the cache line size. This could cause lines to not be addressed when iterating more lines than the cache line size.

  2. The page entry swap logic is missing handling for the TLB invalidation for EL1.

  • Impacts functionality?
  • Impacts security?
  • Breaking change?
  • Includes tests?
  • Includes documentation?

  How This Was Tested

  • Boot on SBSA
  • Boot on physical AArch64 device

  Integration Instructions

  N/A

    </blockquote>
    <hr>
  </details>
  

• [REBASE \& FF] Fix caching issue with page table install and MMU disable @cfernald (#194)
  
  Change Details

    # Move page table installation to assembly and disable MMU

  Commit 49c9032 introduced logic to disable the MMU when changing page tables
  if the geometry of the paging level changes. This is required because the
  TCR and TTBR0 registers are interdependent and cannot be updated atomically.
  However, the current implementation introduces cache issue as the cacheability
  of memory when the MMU is disabled is not well defined. This is particularly
  problematic for the instruction stream and the stack, which leads to unstable
  behavior.

  This commit moves the entire swap of all the relevant registers to a dedicated
  assembly routine, which ensures that the scope of access with the MMU disabled
  is contained. Additionally, the assembly routine will be written-back from
  the cache prior to invocation to ensure the correct code is executed.

  This change opts to always disable the MMU when swapping the page tables,
  even if the paging type is not changing. This is dione for 2 reasons:

  1. The current approach makes brittle assumptions on the configuration of
     the page tables at launch such as TCR and MAIR. While these assumptions are
     true today because this crate follows EDK2 style paging, these are not guaranteed
     to stay aligned. By always disabling the MMU, future incompatibilities will
     not lead to unstable behavior.

  2. Attempting to determine when to disable the MMU adds complexity and edge
     cases and provides very little benefit. This is better avoided.

  Fix incomplete implementation of aarch64 detect_paging_type

  This commit fixes a couple issues in aarch64's detect_paging_type function.

  1. The implementation currently assumes 4kb granules, but does not check it.

  2. The implementation currently does not allow for 5-level paging VA sizes
     other then 52 bits.

  Resolves: #192

  • Impacts functionality?
  • Impacts security?
  • Breaking change?
  • Includes tests?
  • Includes documentation?

  How This Was Tested

  • QEMU SBSA Boot
  • Physical aarch64 platform boot

  Integration Instructions

  N/A

    </blockquote>
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  </details>
  

Full Changelog: v11.0.3...v11.0.4