Rev 3.1. Fab set 20x20_ESC_Rev3.1, verified against board and schematic
(designators, per-LCSC quantities) before release.
Changes since rev3:
- Bulk decoupling bank: 22 x 10 uF 1206 on +BATT/GND, 21 of them PCB-only
(19 CL refs absent from the schematic, CL50/CL51 doubled). The schematic is
deliberately not the BOM for these; the fab set carries all 22. - Board setup normalised to the line standard (0.09/0.09, via 0.35/0.20,
2 oz outer rules in the dru). Zero DRC errors. - Flashing and QC fixture projects added to the repo.
EMC relevance (technical file): input PDN decoupling changed; switching
topology, clocks and I/O filtering untouched. Conducted-emissions margin can
only improve; prior evidence carries with that note.
Assets: JLCPCB fab set, STEP fit-check model, schematic PDF.