OpenESC-30x30 Rev 3.1

Rev 3.1. Fab set 30x30-Rev3.1, verified against board and schematic before
release: the shipped Rev3 export matched no committed board state, this one
is checked mechanically (check_export.py).

Changes since rev3:

• Bulk decoupling bank: 52 x 10 uF 1206 on +BATT/GND, 49 of them PCB-only
  (only C2, C3 and C6 exist in the schematic; 24 added since rev3). The
  schematic is deliberately not the BOM for these; the fab set carries all 52.
• Board setup normalised to the line standard. Zero DRC errors.
• Flashing and QC fixture projects added to the repo.

EMC relevance (technical file): input PDN decoupling changed; switching
topology, clocks and I/O filtering untouched.

Assets: JLCPCB fab set, STEP fit-check model, schematic PDF.

OpenESC-30x30 Rev 3

4-in-1 BLDC ESC, 30.5 x 30.5 mm mounting, 6-layer. Four independent AT32F421G8U7 controllers on AM32. Input range moves to 3S-8S.

Version numbering jumps rev1 to rev3 to align with the rest of the line. There is no rev2 tag for this board.

8S rating

The 3x SMBJ24A input TVS are removed. Their 24 V standoff sits below the 33.6 V a full 8S pack reaches, so on 8S they would have conducted rather than protected. Worth noting they were already marginal on 6S, where a full pack reaches 25.2 V.

There is no input clamp now. The 3S-8S rating rests on bench and flight testing on 8S rather than on a clamp. The envelope is bounded by:

Power MOSFETs	SP40N01GHNK, 40 V VDSS
Gate-drive buck	LMR54406DBVR, 36 V rated, 45 V absolute maximum, 50 V for short transients
Current sense	~330 A full-scale

Anyone repurposing this design on 8S should understand that the 40 V FETs sit 6.4 V above a full pack with no clamp, and that the rating comes from measured behaviour rather than from derating headroom.

Also in this revision

JST SM08B-SRSS-TB 3D model fixed in the project library, board images re-rendered.