SPI flash driver: read JEDEC ID, memory-mapped flash reads#14
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SPI flash driver: read JEDEC ID, memory-mapped flash reads#14
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Data abort handler in startup.S prints fault address, DFSR, and PC over UART instead of silent hang. Switches to SVC mode for valid stack before calling C handler. handle_read uses 32-bit word-aligned access for I/O register regions (0x10000000-0x13000000) since ARM peripherals require word access. Tested on hi3516ev300: FMC CRG=0x02 (clock on), VERSION=0x100, CFG=0x1820 (boot mode, SPI NOR). All registers accessible. Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
Flash controller (FMC) initialization: - Enable clock via CRG register - Switch to normal mode (preserve bootrom config bits) - Set SPI timing parameters - Read JEDEC ID via register-mode command Key fix: FMC I/O buffer is at FLASH_MEM (0x14000000) not FMC_BASE+0x100 on real hardware. U-Boot reads from host->iobase which maps here. Also: data abort handler prints fault address/DFSR/PC over UART. Word-aligned 32-bit I/O register reads prevent data aborts. addr_readable extended for CRG, FMC, SYS_CTRL, and flash regions. Tested on hi3516ev300: JEDEC ef4018 (W25Q128, 16MB), 4KB flash read with CRC32 verified, 64KB at 72 KB/s via auto-baud 921600. Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
In normal mode, FLASH_MEM window shows the FMC I/O buffer (JEDEC ID data). In boot mode, it transparently reads flash content. Must switch back to boot mode after register-mode commands for correct reads. Verified: binwalk finds U-Boot + XZ kernel/rootfs in dump. First bytes are ARM branch instruction (bootrom entry), not JEDEC ID. Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
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Summary
SPI flash driver for the bare-metal agent. Initializes the HiSilicon FMC controller and enables memory-mapped flash reads.
addr_readableextended for FMC, CRG, SYS_CTRL, and flash regionsReal Hardware Results (hi3516ev300, W25Q128 16MB)
37x faster than md.b, CRC32 verified.
Key Findings
FLASH_MEM(0x14000000), NOTFMC_BASE + 0x100on real hardwareTest plan
🤖 Generated with Claude Code