Add NAND flash install support and boot protocol robustness#43
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Add NAND flash install support and boot protocol robustness#43
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Install command: - Add --nand flag to `defib install` for NAND flash devices - Add _NAND_LAYOUT: 1M(boot), 1M(env), 8M(kernel), -(ubi) - Use `nand erase/write/read` commands instead of `sf` when --nand - Accept rootfs.ubi tarballs (NAND uses UBI, not squashfs) - Set mtdparts and bootcmd directly (don't rely on device env macros) - Skip flash read-back CRC verify for NAND (ECC/OOB makes it unreliable) - Longer timeouts for NAND erase/write operations Boot protocol (hisilicon_standard): - Add _rehandshake() after SPL: some SoCs (e.g. hi3516av200) re-send 0x20 bootmode markers after DDR init, requiring a fresh 0xAA before accepting U-Boot HEAD frames - Increase U-Boot HEAD retries to 64 at 150ms timeout (was 16 at 30ms) to handle SoCs that are slow to become ready after DDR init - Make U-Boot TAIL failure non-fatal: some SoCs consider the transfer complete once all bytes declared in HEAD are received and don't ACK the TAIL frame Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
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Summary
--nandflag todefib installfor NAND flash devices (layout, commands, UBI rootfs, direct env setup, longer timeouts, skip NAND read-back CRC)_rehandshake()after SPL for SoCs that re-send 0x20 bootmode markers after DDR init (discovered on hi3516av200)Context
Tested on hi3516av200 with NAND flash. The NAND TFTP flash path works end-to-end (U-Boot + kernel + rootfs all transferred and CRC-verified in RAM). The boot ROM protocol on hi3516av200 differs from hi3516ev300: it requires a second handshake after SPL and doesn't ACK the U-Boot TAIL frame. U-Boot startup after upload on hi3516av200 still needs investigation (separate issue).
Test plan
ruff checkcleanmypy --strictclean🤖 Generated with Claude Code