arm: hisilicon: add hi3516cv200 / hi3518ev20x SoC support (CRG + DT + Kconfig)

arch/arm/boot/dts/hisilicon/Makefile

@@ -20,3 +20,5 @@ dtb-$(CONFIG_ARCH_HI3516DV300) += \
 	hi3516dv300-demb.dtb
 dtb-$(CONFIG_ARCH_HI3516CV300) += \
 	hi3516cv300-demb.dtb
+dtb-$(CONFIG_ARCH_HI3516CV200) += \
+	hi3516cv200-demb.dtb

arch/arm/boot/dts/hisilicon/hi3516cv200-demb.dts

@@ -0,0 +1,59 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (c) 2016 HiSilicon Technologies Co., Ltd.
+ *
+ * Hi3516CV200 DEMO Board (DEMB) reference DT.
+ * Ported from the vendor 4.9 BSP arch/arm/boot/dts/hi3518ev20x-demb.dts.
+ *
+ * Production cameras pair this SoC with single MIPI sensors (IMX291,
+ * SC2135, JXF22, etc.) at 1080p; reference board is a generic eval kit.
+ */
+
+/dts-v1/;
+#include "hi3516cv200.dtsi"
+
+/ {
+	model = "Hisilicon Hi3516CV200 DEMO Board";
+	compatible = "hisilicon,hi3516cv200";
+
+	memory {
+		device_type = "memory";
+		/* 64 MiB DDR @ 0x80000000 — production cameras ship with
+		 * 64 MiB total, kernel gets 32 MiB and the upper 32 MiB
+		 * is reserved for the vendor MMZ media allocator (set via
+		 * `mmz=` in the u-boot bootargs). */
+		reg = <0x80000000 0x4000000>;
+	};
+
+	chosen {
+		bootargs = "mem=32M console=ttyAMA0,115200 root=/dev/mtdblock3 rootfstype=squashfs init=/init";
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&i2c_bus0 {
+	status = "okay";
+};
+
+&spi_bus0 {
+	status = "okay";
+};
+
+&mdio {
+	phy0: ethernet-phy@1 {
+		reg = <1>;
+		/* Most cv200 reference boards use an Internal FE PHY at
+		 * MII address 1. Production boards vary; production DT
+		 * fragments can override via a board-specific overlay. */
+	};
+};
+
+&hisi_femac {
+	phy-handle = <&phy0>;
+	phy-mode = "mii";
+	status = "okay";
+};

arch/arm/boot/dts/hisilicon/hi3516cv200.dtsi

@@ -0,0 +1,234 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (c) 2016 HiSilicon Technologies Co., Ltd.
+ *
+ * Hi3516CV200 / Hi3518EV20x V2 SoC family (ARM926EJ-S, ARMv5TE).
+ * Ported from the vendor 4.9 BSP arch/arm/boot/dts/hi3518ev20x.dtsi
+ * onto the modern dt-bindings + crg- driver scaffold. The register map
+ * matches the vendor SDK byte-for-byte; only the dts-level scaffolding
+ * (skeleton.dtsi removal, clock-frequency on SP804, clock-names on
+ * MDIO, phy-reset-delays on FEMAC) is modernized.
+ *
+ * Sibling SoCs that re-use this dtsi: Hi3518EV200, Hi3518EV201.
+ */
+
+#include <dt-bindings/clock/hi3516cv200-clock.h>
+
+/* skeleton.dtsi was removed in 4.18; root cells set explicitly below. */
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	chosen { };
+
+	aliases {
+		serial0 = &uart0;
+		serial1 = &uart1;
+		serial2 = &uart2;
+		i2c0 = &i2c_bus0;
+		i2c1 = &i2c_bus1;
+		i2c2 = &i2c_bus2;
+		spi0 = &spi_bus0;
+		spi1 = &spi_bus1;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,arm926ej-s";
+			reg = <0>;
+		};
+	};
+
+	vic: interrupt-controller@100d0000 {
+		compatible = "arm,pl190-vic";
+		interrupt-controller;
+		#interrupt-cells = <1>;
+		reg = <0x100d0000 0x1000>;
+	};
+
+	soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		interrupt-parent = <&vic>;
+		ranges;
+
+		/* Vendor names this node "clock" but the analogous block
+		 * on cv300 is called "crg_ctrl" — keep vendor naming so the
+		 * 4.9-era DT (which we want to be a drop-in) parses
+		 * unchanged. The compatible matches the CRG driver's
+		 * CLK_OF_DECLARE / platform_driver match_table. */
+		crg_ctrl: clock@20030000 {
+			compatible = "hisilicon,hi3518ev20x-clock";
+			reg = <0x20030000 0x1000>;
+			#clock-cells = <1>;
+			#reset-cells = <2>;
+		};
+
+		sys_ctrl: system-controller@20050000 {
+			compatible = "hisilicon,hi3518ev20x-sysctrl", "syscon";
+			reg = <0x20050000 0x1000>;
+			#clock-cells = <1>;
+		};
+
+		reboot {
+			compatible = "syscon-reboot";
+			regmap = <&sys_ctrl>;
+			offset = <0x4>;
+			mask = <0xdeadbeef>;
+		};
+
+		dual_timer0: dual_timer@20000000 {
+			compatible = "arm,sp804", "arm,primecell";
+			reg = <0x20000000 0x1000>;
+			interrupts = <3>;
+			/* SP804 driver in 6.x uses clk_get_rate() which returns
+			 * 0 if the clock provider isn't fully initialized when
+			 * timer inits at start_kernel. clock-frequency
+			 * overrides — matches the 3 MHz fixed-rate the sysctrl
+			 * early init registers. */
+			clock-frequency = <3000000>;
+			clocks = <&sys_ctrl HI3516CV200_TIME0_0_CLK>,
+				 <&sys_ctrl HI3516CV200_TIME0_1_CLK>,
+				 <&crg_ctrl HI3516CV200_SYSAPB_CLK>;
+			clock-names = "timer0", "timer1", "apb_pclk";
+		};
+
+		dual_timer1: dual_timer@20010000 {
+			compatible = "arm,sp804", "arm,primecell";
+			reg = <0x20010000 0x1000>;
+			interrupts = <4>;
+			clock-frequency = <3000000>;
+			clocks = <&sys_ctrl HI3516CV200_TIME1_2_CLK>,
+				 <&sys_ctrl HI3516CV200_TIME1_3_CLK>,
+				 <&crg_ctrl HI3516CV200_SYSAPB_CLK>;
+			clock-names = "timer2", "timer3", "apb_pclk";
+			status = "disabled";
+		};
+
+		uart0: uart@20080000 {
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0x20080000 0x1000>;
+			interrupts = <5>;
+			clocks = <&crg_ctrl HI3516CV200_UART0_CLK>;
+			clock-names = "apb_pclk";
+		};
+
+		uart1: uart@20090000 {
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0x20090000 0x1000>;
+			interrupts = <30>;
+			clocks = <&crg_ctrl HI3516CV200_UART1_CLK>;
+			clock-names = "apb_pclk";
+			status = "disabled";
+		};
+
+		uart2: uart@200a0000 {
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0x200a0000 0x1000>;
+			interrupts = <25>;
+			clocks = <&crg_ctrl HI3516CV200_UART2_CLK>;
+			clock-names = "apb_pclk";
+			status = "disabled";
+		};
+
+		i2c_bus0: i2c@200d0000 {
+			compatible = "hisilicon,hisi-i2c-hisilicon";
+			reg = <0x200d0000 0x100>;
+			interrupts = <20>;
+			clocks = <&crg_ctrl HI3516CV200_SYSAPB_CLK>;
+			clock-frequency = <100000>;
+			status = "disabled";
+		};
+
+		i2c_bus1: i2c@20240000 {
+			compatible = "hisilicon,hisi-i2c-hisilicon";
+			reg = <0x20240000 0x100>;
+			interrupts = <20>;
+			clocks = <&crg_ctrl HI3516CV200_SYSAPB_CLK>;
+			clock-frequency = <100000>;
+			status = "disabled";
+		};
+
+		i2c_bus2: i2c@20250000 {
+			compatible = "hisilicon,hisi-i2c-hisilicon";
+			reg = <0x20250000 0x100>;
+			interrupts = <20>;
+			clocks = <&crg_ctrl HI3516CV200_SYSAPB_CLK>;
+			clock-frequency = <100000>;
+			status = "disabled";
+		};
+
+		spi_bus0: spi@200c0000 {
+			compatible = "arm,pl022", "arm,primecell";
+			arm,primecell-periphid = <0x00800022>;
+			reg = <0x200c0000 0x1000>;
+			interrupts = <6>;
+			clocks = <&crg_ctrl HI3516CV200_SPI0_CLK>;
+			clock-names = "apb_pclk";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		spi_bus1: spi@200e0000 {
+			compatible = "arm,pl022", "arm,primecell";
+			arm,primecell-periphid = <0x00800022>;
+			reg = <0x200e0000 0x1000>;
+			interrupts = <7>;
+			clocks = <&crg_ctrl HI3516CV200_SPI1_CLK>;
+			clock-names = "apb_pclk";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		mdio: mdio@10091100 {
+			compatible = "hisilicon,hisi-femac-mdio";
+			reg = <0x10091100 0x10>;
+			/* modern hisi-femac-mdio uses devm_clk_get(dev,"mdio")
+			 * — needs a NAMED clock, not unnamed. */
+			clocks = <&crg_ctrl HI3516CV200_ETH_CLK>;
+			clock-names = "mdio";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		hisi_femac: ethernet@10090000 {
+			compatible = "hisilicon,hi3518ev20x-femac",
+				     "hisilicon,hisi-femac-v2";
+			reg = <0x10090000 0x1000>, <0x10091300 0x200>;
+			interrupts = <12>;
+			clocks = <&crg_ctrl HI3516CV200_ETH_CLK>;
+			resets = <&crg_ctrl 0xec 0>;
+			reset-names = "mac";
+			/* PHY reset delays required by hisi_femac when "phy"
+			 * reset is present. phy-mode + phy-handle set in
+			 * hi3516cv200-demb.dts. */
+			hisilicon,phy-reset-delays-us = <10000 10000 30000>;
+		};
+
+		fmc: flash-memory-controller@10010000 {
+			compatible = "hisilicon,hisi-fmc";
+			reg = <0x10010000 0x1000>, <0x58000000 0x10000>;
+			reg-names = "control", "memory";
+			clocks = <&crg_ctrl HI3516CV200_FMC_CLK>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		pmux: pinmux@200f0000 {
+			compatible = "pinctrl-single";
+			reg = <0x200f0000 0x108>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+			pinctrl-single,register-width = <32>;
+			pinctrl-single,function-mask = <7>;
+		};
+	};
+};

arch/arm/mach-hibvt/Kconfig

@@ -34,6 +34,19 @@ config ARCH_HI3516CV300
 		Support for HiSilicon Hi3516CV300 camera SoC
 		(ARM926EJ-S single-core, ARMv5TE).
 
+config ARCH_HI3516CV200
+	bool "Hisilicon Hi3516CV200 / Hi3518EV20x ARM926EJ-S family"
+	depends on ARCH_MULTI_V5 && CPU_LITTLE_ENDIAN
+	select ARM_VIC
+	select ARM_TIMER_SP804
+	select PINCTRL
+	select COMMON_CLK_HI3516CV200
+	select ARCH_HAS_RESET_CONTROLLER
+	select RESET_CONTROLLER
+	help
+		Support for HiSilicon Hi3516CV200 / Hi3518EV20x V2 camera
+		SoC family (ARM926EJ-S single-core, ARMv5TE).
+
 config ARCH_HI3516CV500
 	bool "Hisilicon Hi3516CV500 Cortex-A7 family"
 	depends on ARCH_MULTI_V7

drivers/clk/hisilicon/Kconfig

@@ -7,6 +7,16 @@ config COMMON_CLK_HI3516CV300
 	help
 	  Build the clock driver for hi3516cv300.
 
+config COMMON_CLK_HI3516CV200
+	tristate "HI3516CV200 / Hi3518EV20x Clock Driver"
+	depends on ARCH_HISI || ARCH_HISI_BVT || COMPILE_TEST
+	select RESET_HISI
+	default ARCH_HI3516CV200
+	help
+	  Build the clock driver for the V2 family — hi3516cv200,
+	  hi3518ev200, hi3518ev201. Ports the vendor 4.9 BSP clock
+	  topology onto the modern crg- platform_driver scaffold.
+
 config COMMON_CLK_HI3519
 	tristate "Hi3519 Clock Driver"
 	depends on ARCH_HISI || ARCH_HISI_BVT || COMPILE_TEST

drivers/clk/hisilicon/Makefile

@@ -9,6 +9,7 @@ obj-$(CONFIG_ARCH_HI3xxx)	+= clk-hi3620.o
 obj-$(CONFIG_ARCH_HIP04)	+= clk-hip04.o
 obj-$(CONFIG_ARCH_HIX5HD2)	+= clk-hix5hd2.o
 obj-$(CONFIG_COMMON_CLK_HI3516CV300)	+= crg-hi3516cv300.o
+obj-$(CONFIG_COMMON_CLK_HI3516CV200)	+= crg-hi3516cv200.o
 obj-$(CONFIG_COMMON_CLK_HI3519)	+= clk-hi3519.o
 obj-$(CONFIG_COMMON_CLK_HI3559A)	+= clk-hi3559a.o
 obj-$(CONFIG_COMMON_CLK_HI3660) += clk-hi3660.o