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MIT-licensed Goldilocks Poseidon2 12-element permutation hardware accelerator. Chisel source and generated SystemVerilog.
Released design
| Item | Scope |
|---|---|
| Computation | Complete 12-element Poseidon2 permutation; seventh-power S-box, 8 full and 22 partial rounds |
| Field and encoding | Goldilocks p = 2^64 - 2^32 + 1; 12 canonical 64-bit elements per state |
| Bundled configuration | t12, 16 interleaved contexts; top GoldilocksPoseidon2 |
| Native boundary | Atomic 12-element ready/valid request and response, with a returned 32-bit tag |
| Other documented configuration | 32 contexts are separately verified; bundled synthesis results cover 16 contexts |
Engineering evidence and integration
Project overview · Native interface · Reproduction · Performance · Synthesis scope · License
Recorded verification scope: The recorded flow cross-checks independent C and Python references and runs regenerated and bundled SV. Six modes distinguish ideal traffic, protocol stalls, reset recovery, an intentional one-bit reference error, isolated latency and disabled-start buffering. In positive 256-task modes every one of the 3,072 result elements is checked; the negative mode must detect its deliberate error.
Integration boundary: This is a state-to-state permutation, not a complete sponge, byte hash, Merkle engine or transcript. Absorption, padding, domain separation and digest extraction remain external. All round constants and linear layers must match the target protocol. Ready/valid handshakes and tags, rather than a fixed response delay, define integration; reset invalidates in-flight work.
Evidence applies to the documented version, configuration and target. Simulation, synthesis and board/silicon measurements are distinct. These are standalone compute blocks, not an end-to-end zero-knowledge prover.
Custom integration and licensing
For optional custom ASIC/FPGA accelerator development and integration, visit OpenRTL Lab. MIT-licensed commercial use does not require a paid engagement. Retain applicable copyright, license and third-party notices.
Release downloads
These downloads provide hardware sources and bundled RTL for this version. Archive annotations and documentation can differ from the online source tree; use the product file list for integration and the linked documents for verification scope.
OpenRTL organization · ZK accelerator catalogue
简体中文
MIT 开源 Goldilocks Poseidon2 十二元素置换硬件加速器，提供 Chisel 源码与生成的 SystemVerilog。
已发布设计
本模块只计算Goldilocks域12元素Poseidon2置换：8完整轮、22部分轮，典型交付16交错上下文。请求和响应各一次传输完整状态并返回32位tag；32上下文有单列验证，但综合结论仅适用于16上下文。它不是完整海绵或Merkle树，吸收、填充、域分离与摘要提取由外部协议负责。
工程证据与集成
项目介绍 · 原生接口 · 复现步骤 · 性能条件 · 综合范围 · 许可
支持配置、数学模型、测试场景、性能条件和综合结论分别以对应文档为准。仿真、综合与板级或硅后实测应区分理解，不能把某一配置的验证结论推广到全部参数或目标。这是独立计算模块，不是端到端零知识证明生成系统。
定制集成与开源许可
如需可选的 ASIC/FPGA 加速器定制开发与集成，请到 OpenRTL Lab 官方网站了解服务与联系方式。MIT 许可代码可免费用于商业用途，保留适用的版权、许可和第三方声明；付费定制与支持是独立、可选的服务。
发布下载
以上下载提供本版本硬件源码与随包 RTL。源码包与在线源码树的注释及文档可能不同；集成使用产品文件清单，验证范围以链接文档为准。