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v1.1.0 — Goldilocks Poseidon2 sponge hashing and digest compression | Goldilocks Poseidon2 海绵哈希与摘要压缩
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MIT-licensed Goldilocks Poseidon2 sponge hashing and digest compression hardware accelerator. Chisel source and generated SystemVerilog.
Released design
| Item | Scope |
|---|---|
| Computation | HASH of field-element messages and COMPRESS2 of two four-element digests |
| Fixed hash profile | Goldilocks Poseidon2 state 12, rate 8, digest 4; documented HASH padding and unpadded COMPRESS2 |
| Bundled configuration | 16 interleaved contexts, maximum message length 4,096 field elements |
| Product top | GoldilocksPoseidon2Sponge; one shared permutation core, not 16 independent cores |
| Native boundary | Tagged task, 8-element message blocks, 4-element digest and completion ready/valid channels |
Engineering evidence and integration
Project overview · Native interface · Reproduction · Performance · Synthesis scope · License
Recorded verification scope: The documented default flow checks independent C/Python references, generated/bundled 16-context products and additional 32-context/8,192-element coverage. Mixed tests include backpressure, reset recovery and deliberate-reference faults; dedicated isolated/sustained tests distinguish HASH and COMPRESS2 performance. Padding and trailing-zero controls explicitly check that HASH of eight elements is not silently treated as COMPRESS2.
Integration boundary: Messages are canonical Goldilocks elements, not arbitrary bytes. Byte encoding, protocol domain separation and tree scheduling remain outside this block. COMPRESS2 consumes exactly eight elements and does not apply HASH padding. Empty HASH, blocked digest/completion and reset have defined semantics. The published synthesis configuration is 16 contexts / 4,096 elements, not every generator capacity or protocol profile.
Evidence applies to the documented version, configuration and target. Simulation, synthesis and board/silicon measurements are distinct. These are standalone compute blocks, not an end-to-end zero-knowledge prover.
Custom integration and licensing
For optional custom ASIC/FPGA accelerator development and integration, visit OpenRTL Lab. MIT-licensed commercial use does not require a paid engagement. Retain applicable copyright, license and third-party notices.
Release downloads
These downloads provide hardware sources and bundled RTL for this version. Archive annotations and documentation can differ from the online source tree; use the product file list for integration and the linked documents for verification scope.
OpenRTL organization · ZK accelerator catalogue
简体中文
MIT 开源 Goldilocks Poseidon2 海绵哈希与摘要压缩硬件加速器，提供 Chisel 源码与生成的 SystemVerilog。
已发布设计
本模块是Poseidon2海绵哈希与双摘要压缩，不只是底层置换。状态12、吸收率8、摘要4，典型16上下文和最长4096域元素消息。HASH按规定填充，COMPRESS2恰好消耗两个四元素摘要且不作HASH填充，两者不能互换。输入不是任意字节；字节编码、协议域分离和树调度由集成方负责。
工程证据与集成
项目介绍 · 原生接口 · 复现步骤 · 性能条件 · 综合范围 · 许可
支持配置、数学模型、测试场景、性能条件和综合结论分别以对应文档为准。仿真、综合与板级或硅后实测应区分理解，不能把某一配置的验证结论推广到全部参数或目标。这是独立计算模块，不是端到端零知识证明生成系统。
定制集成与开源许可
如需可选的 ASIC/FPGA 加速器定制开发与集成，请到 OpenRTL Lab 官方网站了解服务与联系方式。MIT 许可代码可免费用于商业用途，保留适用的版权、许可和第三方声明；付费定制与支持是独立、可选的服务。
发布下载
以上下载提供本版本硬件源码与随包 RTL。源码包与在线源码树的注释及文档可能不同；集成使用产品文件清单，验证范围以链接文档为准。