RV32IMBC RISC-V Core

Single-cycle core written in SystemVerilog, simulated with Verilator, and verified using cocotb testbenches. Instruction decoding is generated from configuration files and the official encodings from the riscv-opcodes project.

The core

RV32IMBC with Zicsr and Zifencei, Machine mode only — misa is 0x40001106. Eighty-five full-width instructions and twenty-six compressed encodings.

Each instruction executes in one cycle. Only two conditions stall the core: a pending memory request and an ongoing division. Both use the same stalled path.

Implemented traps cover illegal instructions, access faults, data alignment faults, ECALL, EBREAK, MRET, and the three Machine-mode interrupts.

What is generated

The configuration describes the ISA; the tools derive the decoder, core constants, and test-program memory images from it.

   config/                        external/riscv-opcodes/
   ├─ core.toml           target   └─ instr_dict.json
   ├─ isa_layout.toml      ISA          official encodings
   ├─ microarchitecture.toml               (mask / match)
   └─ compressed.toml                            │
            │                                    │
            └──────────────┬─────────────────────┘
                           ▼
                  tools/check_data.py     rejects inconsistent
                           │              configurations
                           ▼
                  tools/generate.py
                           │
          ┌────────────────┴────────────────┐
          ▼                                 ▼
   rtl/generated/*.sv              sim/generated/constants.py
   decoder, expander,              same values, for the
   parameter packages              testbench side
          │                                 │
          │        rtl/core/*.sv            │
          │        hand-written             │
          │        datapath                 │
          └────────────────┬────────────────┘
                           ▼
                       run.py
                           │
          ┌────────────────┴────────────────┐
          ▼                                 ▼
   Verilator                        programs/*.s
   model compilation                tools/assemble.py
          │                         → build/programs/*.hex
          └────────────────┬────────────────┘
                           ▼
                    cocotb: 37 targets, 57 tests

Nothing under rtl/generated/ or in sim/generated/ should be edited manually: run.py regenerates these files on every run.

The same principle applies to the assembler: it has no hard-coded instruction encodings and reads the same tables as the hardware. An instruction added to the configuration becomes assemblable without any assembler changes.

Usage

In an environment containing Verilator and cocotb:

python run.py              # all targets
python run.py cpu_muldiv   # a single target
python run.py --generate-only
make test                  # validation, generation, then all tests

To refresh the official encodings after changing the extension list:

python tools/update_riscv_opcodes.py

Project structure

Path	Contents
config/	ISA and simulation-target descriptions
tools/	validation, generation, assembler, and encoding updates
rtl/core/	hand-written datapath
rtl/generated/	generated decoder and packages
rtl/memory/, rtl/top/	behavioral models and simulation top modules
programs/	assembly test programs
sim/tests/	cocotb testbenches

Each target in config/targets.toml associates a top module, a test module, and a source set. Unit targets compile a single module; cpu_* targets compile the complete core with a different program.