v0.1.0 — first public release

D-FINE-cpp v0.1.0

C++/TensorRT inference runtime for the D-FINE object detector. First public release.

Highlights

• Correct on TensorRT. The explicit gather-bilinear deformable-attention export fixes a −10.5 AP
  trap in the stock grid_sample export (TRT compiles it divergently in-context). No plugin, no
  latency cost; full-val mAP matches PyTorch to ≤0.001 AP on all five model sizes.
• FP16 that holds mAP. Strongly-typed FP16 (precision baked into ONNX types, decoder kept FP32):
  −0.2% mAP worst case at 1.3–2.8× the FP32 throughput. The weakly-typed kFP16 builder flag loses a
  fixed 6.8 AP on D-FINE and is not used.
• Frozen single-launch pipeline (intensive-core P1–P3). Opt-in gpu_decode (Zero-D2H decode on
  device), freeze()/FreezeSpec (zero steady-state allocation, VRAM Δ = +0 B over full runs), and
  full_pipeline_graph: H2D → preprocess → inference → decode → D2H replayed as one
  cudaGraphLaunch per frame. Byte-identical to the split path on all five sizes (validated on real
  640×480 COCO images); CPU cost per frame drops to 0.2–0.9 ms (batch-1 dispatch ≈ 0.1 ms).
• Bindings. Stable C ABI (opaque handle, thread-local errors) and a dependency-light Python
  ctypes package + dfine CLI; detections byte-identical to the C++ binary (pytest-verified).
  Custom label sets ride the .json sidecar end to end (class_names).
• Optional letterbox preprocessing. PreprocessSpec (options or sidecar resize field):
  anchor center/topleft, padding value, upscale on/off; boxes are un-mapped and clipped
  automatically, works with the GPU decode and the full-pipeline graph (byte-parity verified).
  Stretch stays the default — it is the training convention and measures ~1.7–2.0 AP better on the
  published weights (trt-files/scripts/letterbox_eval.py); the native CUDA path reproduces the
  host references to +0.0002 AP.

Numbers (RTX 4070 Ti SUPER, COCO val2017 full, e2e)

size	C++ FP16 FPS b1 / b8	mAP (PyTorch ref)
nano	453 / 1206	0.4280 (0.4279)
small	346 / 638	0.5069 (0.5073)
medium	281 / 442	0.5500 (0.5509)
large	228 / 358	0.5723 (0.5724)
xlarge	180 / 246	0.5927 (0.5931)

Full cross-backend tables (PyTorch / ONNXRuntime-GPU / TensorRT-Python / C++), the CUDA-graph and
full-pipeline-graph comparisons, and the per-config mAP matrix are reproducible with
trt-files/scripts/overnight_bench.sh.

Artifacts

• dfine_{n,s,m,l,x}.onnx + dfine_{n,s,m,l,x}_fp16_st.onnx — ready-to-build ONNX exports (raw
  two-output graph, explicit deform core) with .json sidecars. Engines are GPU-arch/TRT-version
  specific: build locally with trt-files/scripts/build_engine.py (see README Quickstart).
• SHA256SUMS — checksums for every artifact.
• dfine-0.1.0-py3-none-linux_x86_64.whl — Python package with bundled libdfine.so (sm_89; needs
  local TensorRT 10.x + CUDA 12 at runtime).
• Demo clips (mp4): side-by-side throughput comparisons rendered by make_demo_gif.py.

Requirements

Linux x86_64, NVIDIA GPU, CUDA 12.x, TensorRT 10.x (validated on 10.13), CMake ≥ 3.24 for
CUDA_ARCHITECTURES=native (≥ 3.20 with an explicit arch). No OpenCV.

Known limitations

• Detection only (instance segmentation shelved — no pretrained seg checkpoints).
• INT8/BF16 rejected: D-FINE's FDR box decode needs FP16-or-better mantissa precision (measured, see
  README precision guide).
• The C ABI does not yet expose gpu_decode/freeze/full_pipeline_graph (C++-only for now).
• Wheel is linux_x86_64/sm_89; other platforms build from source.