Remove native-gates file; update get-qpu-information, qpu-information, and processor-types accordingly

docs/guides/_toc.json

@@ -600,11 +600,7 @@
               "url": "/docs/guides/calibration-jobs"
             },
             {
-              "title": "Native gates and operations",
-              "url": "/docs/guides/native-gates"
-            },
-            {
-              "title": "Dynamic repetition rate execution",
+              "title": "Qubit initialization",
               "url": "/docs/guides/repetition-rate-execution"
             },
             {

docs/guides/execute-on-hardware.mdx

@@ -61,7 +61,6 @@ expectation values of observables corresponding to physical quantities or cost f
 * [QPU information](./qpu-information)
 * [Calibration jobs](./calibration-jobs)
 * [Get QPU information with Qiskit](./get-qpu-information)
-* [Native gates and operations](./native-gates)
 * [Dynamic repetition rate execution](./repetition-rate-execution)
 * [Retired QPUs](./retired-qpus)
 * [Instances](./instances)

docs/guides/get-qpu-information.ipynb

@@ -246,6 +246,37 @@
     "For a full list of attributes, see the [`IBMBackend` API documentation](/docs/api/qiskit-ibm-runtime/ibm-backend)."
    ]
   },
+  {
+   "cell_type": "markdown",
+   "id": "6a055938-0a1d-46ef-ae9c-60a7960d6d73",
+   "metadata": {},
+   "source": [
+    "## Native gates and operations\n",
+    "\n",
+    "Each [processor family](/docs/guides/processor-types) has a native gate set. By default, the QPUs in each family only support running the gates and operations in the native gate set. Thus, every gate in the circuit must be translated (by the transpiler) to the elements of this set.\n",
+    "\n",
+    "You can view the native gates and operations for a QPU either [with Qiskit](#native-gates-with-qiskit), or on the IBM Quantum® Platform [Compute resources page](/docs/guides/qpu-information#native-gates-on-platform).\n",
+    "\n",
+    "<span id=\"native-gates-with-qiskit\"></span>\n",
+    "```python\n",
+    "\n",
+    "from qiskit_ibm_runtime import QiskitRuntimeService\n",
+    "\n",
+    "service = QiskitRuntimeService()\n",
+    "\n",
+    "for backend in service.backends():\n",
+    "    config = backend.configuration()\n",
+    "    if \"simulator\" in config.backend_name:\n",
+    "        continue\n",
+    "    print(f\"Backend: {config.backend_name}\")\n",
+    "    print(f\"    Processor type: {config.processor_type}\")\n",
+    "    print(f\"    Supported instructions:\")\n",
+    "    for instruction in config.supported_instructions:\n",
+    "        print(f\"        {instruction}\")\n",
+    "    print()\n",
+    "```"
+   ]
+  },
   {
    "cell_type": "markdown",
    "id": "48cf020c-24eb-49dd-a417-7196d036b0e8",

docs/guides/processor-types.mdx

@@ -8,6 +8,10 @@ description: Information on IBM Quantum hardware and features of different proce
 
 Processor types are named for the general technology qualities that go into builds, consisting of the family and revision. Family (for example, Heron) refers to the size and scale of circuits possible on the chip. This is primarily determined by the number of qubits and the connectivity graph. Revisions (for example, r3) are design variants within a given family, often leading to performance improvements or tradeoffs.
 
+<Admonition type="tip" title="Native gates and operations">
+To find the native gates and operations of a backend, use [this code](/docs/guides/get-qpu-information#native-gates-with-qiskit). You can see all native gates and operations in [this table](/docs/guides/qpu-information#native-gates).
+</Admonition>
+
 ## Heron
 
 ![Heron processor icon](/docs/images/guides/processor-types/heron.svg)
@@ -18,8 +22,6 @@ At 156 qubits, Heron is an [Eagle](#eagle)-sized upgrade to [Egret](#egret) that
 
 *   [View available Heron processors](https://quantum.cloud.ibm.com/computers?processorType=Heron)
 
-* [Native gates and operations](native-gates): `cz, id, delay, measure, reset, rz, sx, x, if_else, for_loop, switch_case`
-
 <Admonition type="info" title="Revisions">
   `r3` (July 2025) Heron r3 is the result of targeted manufacturing improvements that directly impact coherence, gate fidelity, and readout performance.
 
@@ -47,8 +49,6 @@ See [IBM Quantum breaks the 100‑qubit processor barrier](https://www.ibm.com/q
 
 *   [View available Eagle processors](https://quantum.cloud.ibm.com/computers?processorType=Eagle)
 
-* [Native gates and operations](native-gates): `ecr, id, delay, measure, reset, rz, sx, x, if_else, for_loop, switch_case`
-
 <Admonition type="info" title="Revisions">
   `r3` (December 2022) Eagle r3 is a version of the 127-qubit processor with enhanced coherence properties but otherwise similar design parameters to Eagle r1.
 
@@ -91,7 +91,8 @@ Quantum volume: 128
 
 The Falcon family of devices offers a valuable platform for medium-scale circuits, and also serves as a valuable platform for demonstrating performance and scalability improvements before they’re pushed onto the larger devices.
 
-* [Native gates and operations](native-gates): `cx, id, delay, measure, reset, rz, sx, x, if_else, for_loop, switch_case`
+*   [View available Falcon processors](https://quantum.cloud.ibm.com/computers?processorType=Falcon)
+
 
 <Admonition type="info" title="Revisions">
   `r8` (September 2021) In addition to the features of r5.11, Falcon r8 has enhanced coherence properties.