[Docs] Update devlog up to 250531 about RV32I46F and RV32I46F_5SP's debugging with implementation#114
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ChoiCube84 merged 51 commits intomainfrom May 31, 2025
Merged
[Docs] Update devlog up to 250531 about RV32I46F and RV32I46F_5SP's debugging with implementation#114ChoiCube84 merged 51 commits intomainfrom
ChoiCube84 merged 51 commits intomainfrom
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Update devlog
…plementation and debugging
…face module level design
…e implemented in Instruction Memory
… next_pc freeze issue
…calculation implementation
… Documentize 46F Architecture specification
…d draft top module design and test plan
…micro opcode structure
…nch Predictor design start
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2025.05.18. 12:01.
RV32I46F complete.
2025.05.28. 00:54.
RV32I46F_5SP complete.
Waveforms . Up is 5-Stage Pipelined super scalar architecture and below is Scalar architecture.