[Feat] Add fpga directory by adding Dhrystone and Demo FPGA verification Vivado project file

[T410N]

Added fpga/ directory

This directory contains :

• RV32I46F_5SP core FPGA Verification Demo project file
  • Vivado Project File (.xpr)
  • 46F5SP_SoC Design's RTL code
    • UART TX
    • Button and LED interfaces
    • Button signal debouncer module
    • Debugger module
  • Demo Instructions with Trap Handler integrated in Instruction Memory

---

• RV32I46F_5SP core FPGA Performance Evaluation project file
  • Vivado Project File (.xpr)
  • 46F5SP_SoC Design's RTL code
    • UART TX
    • Button and LED interfaces
    • Button signal debouncer module
    • Debugger module
    • Benchmark Controller for calculating Dhrystone performance
  • Dhrystone Instructions integrated in Instruction Memory and Data Memory.
    (RV32I, ilp32: riscv32-unknown-elf-gcc compiled Dhrystone)

⚠️ Important Note

Some files contain absolute paths in include statements:
Such as :

`include "source_locations/a/b/c/source_name.v"

Please update these paths to match your project structure.

[ChoiCube84]

Nice work!