HK MLA: MI35x m16x8 retune, new m16x4 kernel, page_size + mask support - #3072
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Pull request overview
This PR extends and retunes the HK MLA decode path for MI3xx/MI35x by adding page-size support, adding causal-mask (“MTP”) shape coverage, introducing MI35x-specific kernels (including a new m16x4 variant), and plumbing metadata/dispatch changes end-to-end (with experimental gating via AITER_ENABLE_EXPERIMENTAL).
Changes:
- Add variable
page_sizesupport and new experimental MTP shapes (nh16/32/64 variants) in metadata + Python dispatch/tests. - Introduce new/retuned HK decode kernels: MI3xx m16x8, MI35x m16x8 retune, and new MI35x m16x4 (occupancy=2) plus updated softmax/util helpers.
- Update hk decode entrypoint routing (
hk_decode_fwd.cu) and JIT config / HipKittens pin.
Reviewed changes
Copilot reviewed 14 out of 14 changed files in this pull request and generated 5 comments.
Show a summary per file
| File | Description |
|---|---|
| op_tests/test_mla_persistent.py | Extends test dispatch gating and passes page_size into metadata; fixes kv_last_page_lens handling comment. |
| csrc/kernels/mla/metadata/v1_2_device.cuh | Adds experimental gating, cluster multiplier for m16x4 occupancy=2, and expands supported-shape logic. |
| csrc/kernels/mla/hk/mi3xx_v32_fwd_decode_m16x8_fp8_fp8.cuh | New MI3xx HK decode kernel (m16x8 fp8/fp8) with page-size + causal mask handling. |
| csrc/kernels/mla/hk/mi3xx_v32_fwd_decode_h128_fp8_fp8.cuh | Removes the prior h128-specific kernel implementation (superseded by m16x8 path). |
| csrc/kernels/mla/hk/mi35x_v32_fwd_decode_m16x8_fp8_fp8.cuh | New MI35x-tuned HK decode kernel (m16x8 fp8/fp8) with kBlockN=64 and PV rescale changes. |
| csrc/kernels/mla/hk/mi35x_v32_fwd_decode_m16x4_fp8_fp8.cuh | New MI35x HK decode kernel (m16x4 fp8/fp8), occupancy=2, product-64 shapes. |
| csrc/kernels/mla/hk/hk_mla_utils.cuh | Refactors shared HK traits/params/helpers; introduces HIP_CALL and expands utility functions. |
| csrc/kernels/mla/hk/hk_mla_softmax.cuh | Adds 16-VGPR softmax scaling helpers and switches lane/warp helpers to opus. |
| csrc/kernels/mla/hk_decode_fwd.cu | Updates HK decode entrypoint to route by (num_head * max_seqlen_q) and GPU arch to new kernels. |
| aiter/ops/attention.py | Adjusts metadata sizing for m16x4 occupancy=2 and adds experimental MTP shape recognition. |
| aiter/mla.py | Updates Python-side gating/dispatch to HK kernels for product-128 and product-64 shapes (experimental). |
| aiter/jit/optCompilerConfig.json | Updates module_hk_mla source list to the new MI3xx kernel header. |
| aiter/jit/core.py | Updates pinned HipKittens commit used by the JIT build system. |
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Add mtp support to HK MLA. Now HK MLA nh128 is renamed as m16x8. It supports: * nh128 + mtp=0 * nh64 + mtp=1 * nh32 + mtp=3 * nh16 + mtp=7 bug fix replace ckt with opus remove mla_dummy dropped kCheckBoundary template parameter Save for 20260421. draft of page size > 1. bug fix for page size > 1 fix TORCH_CHECK Mi35x branch Introduce KVMv3 and use it only in mi35x pipeline. Adjust setprio. Works on MI350 Adjust comments in hk_mla_buffer_managers.cuh draft of using ds_read_tr. fix new pv loop for mi35x adjust pv pipeline adjust pv pipeline part2 overlap packing 4fp32 to fp8 with the load_transposed_v_to_gpr overlap pv mfma and scale oaccu wa for v_pk vs. mfma reorder inst. best known order for MI350 rename buffer manangers 1st draft of m16x4 Adjust params of HkMlaDecodeFwdTraits fix asm regression blockN=64 part.1 blockN=64 part.2 bug fix bug fix 2 bug fixed. MI35x nh128 blockN=64 pass Tuned m16x8 blockN=64 setprio adjust setprio m16x4 + kBlockN=64 make use of occupancy=2 for m16x4 t o Fix the issues raised by Copilot.
valarLip
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May 11, 2026
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Summary
Two tracks of HK MLA work landing together:
1. MI30x kernel: feature additions
nh64+mtp1,nh32+mtp3,nh16+mtp7alongside the existingnh128+mtp0.The existing kernel is designed for MI30x and is functional on MI35x.
2. MI35x: dedicated m16x8 + new m16x4
The new MI35x m16x8 kernel inherits from the MI30x kernel and is fine-tuned for MI35x:
KvManager8bitsV3to useds_read_trfor KV loads.kBlockNbumped 32 → 64.oaccuinterleaved with the PV GEMM.ds_permute_b32withv_permlane16/32_swap_b32.The new m16x4 kernel targets
num_heads * max_seqlen_qo == 64shapes (covers(64,1),(32,2),(16,4)) on MI35x. It mirrors the m16x8 design at kBlockN=64 with Q/KV LDS overlap so it can run at occupancy=2; metadata and launch grid are plumbed end-to-end (get_mla_metadata_v1_2_device,get_mla_metadata_info_v1, and the kernel launch all agree on2*num_cuclusters when m16x4 is dispatched). m16x4 dispatch and the cluster doubling are gated onAITER_ENABLE_EXPERIMENTAL=1.Performance — m16x8 (
-n 128,1, MI355)Measured against the previous HK build and the ASM reference for this shape (note: ASM v3 does not exist for m16x8). Highlights:
m16x4 vs ASM v3
The new m16x4 kernel currently runs ~20% slower than ASM v3 on the m16x4-eligible shapes. It is included here to land the kBlockN=64 + occupancy=2 plumbing and unblock further tuning; closing the gap to ASM v3 is tracked as follow-up work and m16x4 is gated behind
AITER_ENABLE_EXPERIMENTALso production traffic is unaffected.Test Results:
The following is test results of
-n 128,1on MI355.