AITER v0.1.21.post2

AITER v0.1.21.post2 - post release

Post release on top of the release/v0.1.21.post2 release line.

Diff base: v0.1.21.post1

Wheels

Prebuilt manylinux_2_28 wheels, GPU_ARCHS=gfx942;gfx950:

ROCm	Python	Wheel
ROCm 7.0	cp310	amd_aiter-0.1.21.post2+rocm7.0.manylinux.2.28-cp310-cp310-manylinux_2_27_x86_64.manylinux_2_28_x86_64.whl
ROCm 7.0	cp312	amd_aiter-0.1.21.post2+rocm7.0.manylinux.2.28-cp312-cp312-manylinux_2_27_x86_64.manylinux_2_28_x86_64.whl
ROCm 7.1	cp310	amd_aiter-0.1.21.post2+rocm7.1.manylinux.2.28-cp310-cp310-manylinux_2_27_x86_64.manylinux_2_28_x86_64.whl
ROCm 7.1	cp312	amd_aiter-0.1.21.post2+rocm7.1.manylinux.2.28-cp312-cp312-manylinux_2_27_x86_64.manylinux_2_28_x86_64.whl
ROCm 7.2	cp310	amd_aiter-0.1.21.post2+rocm7.2.manylinux.2.28-cp310-cp310-manylinux_2_27_x86_64.manylinux_2_28_x86_64.whl
ROCm 7.2	cp312	amd_aiter-0.1.21.post2+rocm7.2.manylinux.2.28-cp312-cp312-manylinux_2_27_x86_64.manylinux_2_28_x86_64.whl

What's Changed

Changes

• [Triton/Gluon] Add config-aware repr to the rope and normalization kernels by @Boss2002n in #5099
• [Triton/Gluon] Add config-aware repr to the quant kernels by @Boss2002n in #5100
• [CI] CI: use app token for release refs by @gyohuangxin in #5198
• [CI] CI: respect docker login input in release builds by @gyohuangxin in #5201
• [Triton/Gluon] [HIP] [CK] Remove obsolete availability helpers by @coderfeli in #5116
• [FlyDSL] Add FlyDSL Radix-Select TopK Path to the Existing Per-Row Decode Interface by @lirui927 in #5011
• [CI] CI: set release publish repository context by @gyohuangxin in #5204
• [HIP] Add fused SiTUv2 activation + per-token FP8 quant kernel by @XiaobingSuper in #5081
• [Docs] docs: update README by @shengnxu in #5073
• [CK] [FlyDSL] Retune Kimi-K3 a16w4 MoE tile geometry by @amd-wsung102 in #5118
• [Config] tune a8w8 gemm with 64-step m for k3 by @gbyu-amd in #5197
• [CI] CI: add extended test workflow by @gyohuangxin in #4458
• [CI] Run extended test dispatch on internal runner by @gyohuangxin in #5205
• Fix stale TopK availability checks by @vorapolsiloai in #5210
• [CI] Extended tests client_payload change by @leo-automation in #5209
• [Triton/Gluon] Move the sage-attention launch params into the config tree by @Boss2002n in #5106
• [Triton/Gluon] moe_gemm_a4w4 num_warps 8 -> 4 for block_m != 16 tile by @nidal567 in #5189
• [Docs] Update docs for the single nested config layout by @Boss2002n in #5085
• [skills] Add kernel PR validation and structural D9 scanning (supersedes #4870) by @zhiding512 in #5142
• [AMD][DSV4] Fix(fmoe): fuse stage-1 fp8 quant on the heuristic FlyDSL fallback by @karverma-amd in #4994
• [Bugfix] Make _fold_seqlen_indptr cudagraph-safe (avoid scalar H2D copy) by @micah-wil in #5202
• [FlyDSL] Relax GDR decode test mismatch tolerance by @xytpai in #5215
• [HIP] Extend fused QK norm for MiniMax-M3 by @weitliao in #5143
• Revert "[AMD][DSV4] Fix(fmoe): fuse stage-1 fp8 quant on the heuristic FlyDSL fallback" by @valarLip in #5227
• [Triton/Gluon] [CI] Add fused KDA decode kernel (conv1d + recurrence + gated RMSNorm) by @mengfei-jiang in #4712
• [HIP] fix(mla/metadata): scale the auto KV-split count with the machine width by @whx-sjtu in #5212
• [Triton/Gluon] Add repr to DiT fused kernels + Cover round_intermediate in tests by @brunomazzottiamd in #5154
• [HIP] [FlyDSL] Refactor gfx950 A16W16 GEMM with centralized policy selection and tuning by @xytpai in #5145
• [Triton/Gluon] [GFX9] [GFX12] EP MOE changes by @k50112113 in #4500

New Contributors

• @amd-wsung102 made their first contribution in #5118
• @weitliao made their first contribution in #5143
• @whx-sjtu made their first contribution in #5212

Full Changelog: v0.1.21.post1...v0.1.21.post2