merge main into amd-staging #346
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Generate a usage error instead of asserting.
…llvm#162476) wrapping Shrink wrapping treats a load from constant pool as a stack access. This is not correct. Constants are basically stored in read only section AFAIU. This prevents shrink wrapping from kicking in. (Related to PR llvm#160257. PR llvm#160257 will be closed.)
…164393) As far as I understand, constant pool access does not access stack and accesses read-only memory. This patch considers constant pool access as non-stack access allowing shrink wrapping to happen in the concerned test. We should be seeing perf improvement with povray benchmark from SPEC17(around 12% with -flto -Ofast) after this patch. An NFC PR llvm#162476 already exists to upload the test before the patch but approval has got delayed. So, as @davemgreen suggested in that PR, I have uploaded the test and patch in this single PR to show how test looks like.
This patch implements the speculative devirtualization feature in the LLVM backend. It handles the case of single implementation devirtualization where there is a single possible callee of a virtual function. - Add cl::opt 'devirtualize-speculatively' to enable it. - Flag is disabled by default. - It works regardless of the visibility of the object. - Not enabled for LTO for now.
LD1Rv8b only supports a base register but the DAG is matched using am_indexed8 with the offset it finds silently dropped. I've also fixed a couple of immediate operands types inconsistencies that don't manifest as bugs because their incorrect scaling is overriden by the complex pattern and MachineInstr that are correct and thus there's nothing to test.
It also separates the `ProtocolRequestsTests` from `ProtocolTypesTests` as I did not want to increase the work in llvm#144595
This PR fixes a handful of latency and uop changes between Znver3 and Znver4 that were otherwise copied from Znver3. Latency and uop values listed that matched Zen3 on uops.info were updated to those for Zen4. Includes: BSF/BSR, DIV, TZCNT, CLMUL, PCMPISTRM, VALIGN, VPERM
The abd nodes do not perform the same as abs(x-y), although they are often mistaken to do so. They extend into a larger bit size before performing the sub / abs and so produce different results. Update the description of the instruction to avoid misunderstandings.
…tore / load intrinsics (llvm#163573) This patch adds several tests identifying potential opportunities for eliminating dead stores and redundant loads when using the `llvm.matrix.column.major.store.*` and `llvm.matrix.column.major.load.*` intrinsics. PR: llvm#163573
Move the `AllocTokenMax` from `CodeGenOptions` and introduces a new `AllocTokenMode` to `LangOptions`. Note, `-falloc-token-mode=` deliberately remains an internal experimental option. This refactoring is necessary because these options influence frontend behavior, specifically constexpr evaluation of `__builtin_infer_alloc_token`. Placing them in `LangOptions` makes them accessible during semantic analysis, which occurs before codegen.
Was going through Dockerfiles to see where we are missing FROM lines with fully qualified names and came across this one. I think it is safe to say it has not been used in a very long time or maintained at all since then since it still tries to download the source tree using svn. Given that, delete it to lower support surface slightly.
An assertion failed when Polly was registering for the pass manager which assumed that there would be only Polly passes. Since this does not need to be the case, re-apply with the assert removed. Includes a non-Polly change to trigger the premerge CI to trigger check-llvm which failed for 0b9a7b8, but pre-merge did not catch.
…164298) These two operations are expressed as LHS = LHS || RHS, for any construct in which that is valid. Fortunately, the mechanism for codegen from previous reduction works great for this, so it saw minimal changes. This is the last of the reduction construct lowering.
8d29d09 exposed a crash due to incorrectly trying to handle masked interleave recipes. For now, the current code does not support masked interleave recipes. Bail out for them.
The OpenACC spec allows only `v = x` form for atomic-read, and only when both are L-values. The result is this ends up being a pretty trivial patch, however it adds a decent amount of infrastructure for the other forms of atomic. Additionally, the 3.4 spec starts allowing the 'if' clause on atomic, which has recently been added to the ACC dialect. This patch also ensures that can be lowered as well. Extensive testing of this feature was done on other clauses, so there isn't much further work/testing to be done for it.
… with dimensions of size 0 (llvm#163791) Runtime verification on Linalg structured ops unconditionally computed `end - 1` to determine the last iteration index before composing indexing maps. This caused spurious "negative index" assertion failures while operating on empty tensors (tensors with a dimension of size 0). The issue occurs because: 1. Empty tensors create loop ranges [0, 0) with zero trip count 2. Computing end - 1 = 0 - 1 = -1 creates a fictitious negative index 3. The negative index check triggers even though no loop iterations occur The fix is to guard all runtime verification with a check that ensures all loop ranges are non-empty (start < end) before performing any index arithmetic. Example MLIR that previously failed: ```mlir func.func @fill_empty() -> tensor<0xi32> { %c0 = arith.constant 0 : i32 %empty = tensor.empty() : tensor<0xi32> %filled = linalg.fill ins(%c0 : i32) outs(%empty : tensor<0xi32>) -> tensor<0xi32> return %filled : tensor<0xi32> } ``` --------- Co-authored-by: Hanumanth Hanumantharayappa <hhanuman@ah-hhanuman-l.dhcp.mathworks.com>
A bit of debug info maintenaince for llvm#147540.
Reland PR llvm#162352. Fix by excluding SI_PC_ADD_REL_OFFSET from instructions that set SCC = DST!=0. Passes check-libc-amdgcn-amd-amdhsa now. Distribution of instructions that allowed a redundant S_CMP to be deleted in check-libc-amdgcn-amd-amdhsa test: ``` S_AND_B32 485 S_AND_B64 47 S_ANDN2_B32 42 S_ANDN2_B64 277492 S_CSELECT_B64 17631 S_LSHL_B32 6 S_OR_B64 11 ``` --------- Signed-off-by: John Lu <John.Lu@amd.com> Co-authored-by: Matt Arsenault <arsenm2@gmail.com>
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dpalermo
approved these changes
Oct 22, 2025
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