merge main into amd-staging

compiler-rt/lib/nsan/tests/NSanUnitTest.cpp

@@ -43,8 +43,8 @@ template <typename FT, auto next> void TestFT() {
   ASSERT_EQ(GetULPDiff<FT>(-X, -Y), 3);
 
   // Values with larger differences.
-  static constexpr const __sanitizer::u64 MantissaSize =
-      __sanitizer::u64{1} << FTInfo<FT>::kMantissaBits;
+  static constexpr const __uint128_t MantissaSize =
+      __uint128_t{1} << FTInfo<FT>::kMantissaBits;
   ASSERT_EQ(GetULPDiff<FT>(1.0, next(2.0, 1.0)), MantissaSize - 1);
   ASSERT_EQ(GetULPDiff<FT>(1.0, 2.0), MantissaSize);
   ASSERT_EQ(GetULPDiff<FT>(1.0, next(2.0, 3.0)), MantissaSize + 1);
@@ -57,11 +57,6 @@ TEST(NSanTest, Double) {
   TestFT<double, static_cast<double (*)(double, double)>(nextafter)>();
 }
 
-TEST(NSanTest, Float128) {
-  // Very basic tests. FIXME: improve when we have nextafter<__float128>.
-  ASSERT_EQ(GetULPDiff<__float128>(0.0, 0.0), 0);
-  ASSERT_EQ(GetULPDiff<__float128>(-0.0, 0.0), 0);
-  ASSERT_NE(GetULPDiff<__float128>(-0.01, 0.01), kMaxULPDiff);
-}
+TEST(NSanTest, Float128) { TestFT<__float128, nextafterf128>(); }
 
 } // end namespace __nsan

lldb/test/API/driver/stdio_closed/TestDriverWithClosedSTDIO.py

@@ -8,7 +8,9 @@
 import os
 import sys
 import socket
-import fcntl
+
+if os.name != "nt":
+    import fcntl
 
 import lldbsuite.test.lldbutil as lldbutil
 from lldbsuite.test.lldbtest import *

lldb/test/Shell/SymbolFile/PDB/function-nested-block.test

@@ -1,7 +1,9 @@
 REQUIRES: system-windows, lld
 RUN: %build --compiler=clang-cl --nodefaultlib --output=%t.exe %S/Inputs/FunctionNestedBlockTest.cpp
-RUN: lldb-test symbols -find=function -file FunctionNestedBlockTest.cpp -line 4 %t.exe | FileCheck --check-prefix=CHECK-FUNCTION %s
-RUN: lldb-test symbols -find=block -file FunctionNestedBlockTest.cpp -line 4 %t.exe | FileCheck --check-prefix=CHECK-BLOCK %s
+RUN: env LLDB_USE_NATIVE_PDB_READER=0 lldb-test symbols -find=function -file FunctionNestedBlockTest.cpp -line 4 %t.exe | FileCheck --check-prefix=CHECK-FUNCTION %s
+RUN: env LLDB_USE_NATIVE_PDB_READER=0 lldb-test symbols -find=block -file FunctionNestedBlockTest.cpp -line 4 %t.exe | FileCheck --check-prefix=CHECK-BLOCK %s
+RUN: env LLDB_USE_NATIVE_PDB_READER=1 lldb-test symbols -find=function -file FunctionNestedBlockTest.cpp -line 4 %t.exe | FileCheck --check-prefix=CHECK-FUNCTION %s
+RUN: env LLDB_USE_NATIVE_PDB_READER=1 lldb-test symbols -find=block -file FunctionNestedBlockTest.cpp -line 4 %t.exe | FileCheck --check-prefix=CHECK-BLOCK %s
 
 CHECK-FUNCTION: Found 1 functions:
 CHECK-FUNCTION: name = "main"

llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h

@@ -356,7 +356,7 @@ class LegalizationArtifactCombiner {
     // trunc(ext x) -> x
     ArtifactValueFinder Finder(MRI, Builder, LI);
     if (Register FoundReg =
-            Finder.findValueFromDef(DstReg, 0, DstTy.getSizeInBits())) {
+            Finder.findValueFromDef(DstReg, 0, DstTy.getSizeInBits(), DstTy)) {
       LLT FoundRegTy = MRI.getType(FoundReg);
       if (DstTy == FoundRegTy) {
         LLVM_DEBUG(dbgs() << ".. Combine G_TRUNC(G_[S,Z,ANY]EXT/G_TRUNC...): "
@@ -641,10 +641,11 @@ class LegalizationArtifactCombiner {
       Register SrcReg = Concat.getReg(StartSrcIdx);
       if (InRegOffset == 0 && Size == SrcSize) {
         CurrentBest = SrcReg;
-        return findValueFromDefImpl(SrcReg, 0, Size);
+        return findValueFromDefImpl(SrcReg, 0, Size, MRI.getType(SrcReg));
       }
 
-      return findValueFromDefImpl(SrcReg, InRegOffset, Size);
+      return findValueFromDefImpl(SrcReg, InRegOffset, Size,
+                                  MRI.getType(SrcReg));
     }
 
     /// Given an build_vector op \p BV and a start bit and size, try to find
@@ -759,15 +760,17 @@ class LegalizationArtifactCombiner {
       if (EndBit <= InsertOffset || InsertedEndBit <= StartBit) {
         SrcRegToUse = ContainerSrcReg;
         NewStartBit = StartBit;
-        return findValueFromDefImpl(SrcRegToUse, NewStartBit, Size);
+        return findValueFromDefImpl(SrcRegToUse, NewStartBit, Size,
+                                    MRI.getType(SrcRegToUse));
       }
       if (InsertOffset <= StartBit && EndBit <= InsertedEndBit) {
         SrcRegToUse = InsertedReg;
         NewStartBit = StartBit - InsertOffset;
         if (NewStartBit == 0 &&
             Size == MRI.getType(SrcRegToUse).getSizeInBits())
           CurrentBest = SrcRegToUse;
-        return findValueFromDefImpl(SrcRegToUse, NewStartBit, Size);
+        return findValueFromDefImpl(SrcRegToUse, NewStartBit, Size,
+                                    MRI.getType(SrcRegToUse));
       }
       // The bit range spans both the inserted and container regions.
       return Register();
@@ -799,7 +802,7 @@ class LegalizationArtifactCombiner {
 
       if (StartBit == 0 && SrcType.getSizeInBits() == Size)
         CurrentBest = SrcReg;
-      return findValueFromDefImpl(SrcReg, StartBit, Size);
+      return findValueFromDefImpl(SrcReg, StartBit, Size, SrcType);
     }
 
     /// Given an G_TRUNC op \p MI and a start bit and size, try to find
@@ -819,14 +822,14 @@ class LegalizationArtifactCombiner {
       if (!SrcType.isScalar())
         return CurrentBest;
 
-      return findValueFromDefImpl(SrcReg, StartBit, Size);
+      return findValueFromDefImpl(SrcReg, StartBit, Size, SrcType);
     }
 
     /// Internal implementation for findValueFromDef(). findValueFromDef()
     /// initializes some data like the CurrentBest register, which this method
     /// and its callees rely upon.
     Register findValueFromDefImpl(Register DefReg, unsigned StartBit,
-                                  unsigned Size) {
+                                  unsigned Size, LLT DstTy) {
       std::optional<DefinitionAndSourceRegister> DefSrcReg =
           getDefSrcRegIgnoringCopies(DefReg, MRI);
       MachineInstr *Def = DefSrcReg->MI;
@@ -847,7 +850,7 @@ class LegalizationArtifactCombiner {
         }
         Register SrcReg = Def->getOperand(Def->getNumOperands() - 1).getReg();
         Register SrcOriginReg =
-            findValueFromDefImpl(SrcReg, StartBit + DefStartBit, Size);
+            findValueFromDefImpl(SrcReg, StartBit + DefStartBit, Size, DstTy);
         if (SrcOriginReg)
           return SrcOriginReg;
         // Failed to find a further value. If the StartBit and Size perfectly
@@ -868,6 +871,12 @@ class LegalizationArtifactCombiner {
       case TargetOpcode::G_ZEXT:
       case TargetOpcode::G_ANYEXT:
         return findValueFromExt(*Def, StartBit, Size);
+      case TargetOpcode::G_IMPLICIT_DEF: {
+        if (MRI.getType(DefReg) == DstTy)
+          return DefReg;
+        MIB.setInstrAndDebugLoc(*Def);
+        return MIB.buildUndef(DstTy).getReg(0);
+      }
       default:
         return CurrentBest;
       }
@@ -882,10 +891,10 @@ class LegalizationArtifactCombiner {
     /// at position \p StartBit with size \p Size.
     /// \returns a register with the requested size, or an empty Register if no
     /// better value could be found.
-    Register findValueFromDef(Register DefReg, unsigned StartBit,
-                              unsigned Size) {
+    Register findValueFromDef(Register DefReg, unsigned StartBit, unsigned Size,
+                              LLT DstTy) {
       CurrentBest = Register();
-      Register FoundReg = findValueFromDefImpl(DefReg, StartBit, Size);
+      Register FoundReg = findValueFromDefImpl(DefReg, StartBit, Size, DstTy);
       return FoundReg != DefReg ? FoundReg : Register();
     }
 
@@ -904,7 +913,8 @@ class LegalizationArtifactCombiner {
           DeadDefs[DefIdx] = true;
           continue;
         }
-        Register FoundVal = findValueFromDef(DefReg, 0, DestTy.getSizeInBits());
+        Register FoundVal =
+            findValueFromDef(DefReg, 0, DestTy.getSizeInBits(), DestTy);
         if (!FoundVal)
           continue;
         if (MRI.getType(FoundVal) != DestTy)
@@ -923,7 +933,7 @@ class LegalizationArtifactCombiner {
 
     GUnmerge *findUnmergeThatDefinesReg(Register Reg, unsigned Size,
                                         unsigned &DefOperandIdx) {
-      if (Register Def = findValueFromDefImpl(Reg, 0, Size)) {
+      if (Register Def = findValueFromDefImpl(Reg, 0, Size, MRI.getType(Reg))) {
         if (auto *Unmerge = dyn_cast<GUnmerge>(MRI.getVRegDef(Def))) {
           DefOperandIdx =
               Unmerge->findRegisterDefOperandIdx(Def, /*TRI=*/nullptr);
@@ -1288,12 +1298,19 @@ class LegalizationArtifactCombiner {
     // for N >= %2.getSizeInBits() / 2
     //    %3 = G_EXTRACT %1, (N - %0.getSizeInBits()
 
+    Register DstReg = MI.getOperand(0).getReg();
     Register SrcReg = lookThroughCopyInstrs(MI.getOperand(1).getReg());
     MachineInstr *MergeI = MRI.getVRegDef(SrcReg);
+    if (MergeI && MergeI->getOpcode() == TargetOpcode::G_IMPLICIT_DEF) {
+      Builder.setInstrAndDebugLoc(MI);
+      Builder.buildUndef(DstReg);
+      UpdatedDefs.push_back(DstReg);
+      markInstAndDefDead(MI, *MergeI, DeadInsts);
+      return true;
+    }
     if (!MergeI || !isa<GMergeLikeInstr>(MergeI))
       return false;
 
-    Register DstReg = MI.getOperand(0).getReg();
     LLT DstTy = MRI.getType(DstReg);
     LLT SrcTy = MRI.getType(SrcReg);
 

llvm/include/llvm/IR/IRBuilder.h

@@ -2191,7 +2191,7 @@ class IRBuilderBase {
                       FMFSource);
   }
   Value *CreatePtrToAddr(Value *V, const Twine &Name = "") {
-    return CreateCast(Instruction::PtrToInt, V,
+    return CreateCast(Instruction::PtrToAddr, V,
                       BB->getDataLayout().getAddressType(V->getType()), Name);
   }
   Value *CreatePtrToInt(Value *V, Type *DestTy,

llvm/lib/Target/AArch64/AArch64.h

@@ -60,7 +60,7 @@ FunctionPass *createAArch64CleanupLocalDynamicTLSPass();
 FunctionPass *createAArch64CollectLOHPass();
 FunctionPass *createSMEABIPass();
 FunctionPass *createSMEPeepholeOptPass();
-FunctionPass *createMachineSMEABIPass();
+FunctionPass *createMachineSMEABIPass(CodeGenOptLevel);
 ModulePass *createSVEIntrinsicOptsPass();
 InstructionSelector *
 createAArch64InstructionSelector(const AArch64TargetMachine &,

llvm/lib/Target/AArch64/AArch64.td

@@ -133,6 +133,8 @@ include "AArch64SchedNeoverseN2.td"
 include "AArch64SchedNeoverseN3.td"
 include "AArch64SchedNeoverseV1.td"
 include "AArch64SchedNeoverseV2.td"
+include "AArch64SchedNeoverseV3.td"
+include "AArch64SchedNeoverseV3AE.td"
 include "AArch64SchedOryon.td"
 
 include "AArch64Processors.td"

llvm/lib/Target/AArch64/AArch64Processors.td

@@ -1272,11 +1272,11 @@ def : ProcessorModel<"cortex-x2", NeoverseV2Model, ProcessorFeatures.X2,
                      [TuneX2]>;
 def : ProcessorModel<"cortex-x3", NeoverseV2Model, ProcessorFeatures.X3,
                      [TuneX3]>;
-def : ProcessorModel<"cortex-x4", NeoverseV2Model, ProcessorFeatures.X4,
+def : ProcessorModel<"cortex-x4", NeoverseV3Model, ProcessorFeatures.X4,
                      [TuneX4]>;
-def : ProcessorModel<"cortex-x925", NeoverseV2Model, ProcessorFeatures.X925,
+def : ProcessorModel<"cortex-x925", NeoverseV3Model, ProcessorFeatures.X925,
                      [TuneX925]>;
-def : ProcessorModel<"gb10", NeoverseV2Model, ProcessorFeatures.GB10,
+def : ProcessorModel<"gb10", NeoverseV3Model, ProcessorFeatures.GB10,
                      [TuneX925]>;
 def : ProcessorModel<"grace", NeoverseV2Model, ProcessorFeatures.Grace,
                      [TuneNeoverseV2]>;
@@ -1295,9 +1295,9 @@ def : ProcessorModel<"neoverse-v1", NeoverseV1Model,
                      ProcessorFeatures.NeoverseV1, [TuneNeoverseV1]>;
 def : ProcessorModel<"neoverse-v2", NeoverseV2Model,
                      ProcessorFeatures.NeoverseV2, [TuneNeoverseV2]>;
-def : ProcessorModel<"neoverse-v3", NeoverseV2Model,
+def : ProcessorModel<"neoverse-v3", NeoverseV3Model,
                      ProcessorFeatures.NeoverseV3, [TuneNeoverseV3]>;
-def : ProcessorModel<"neoverse-v3ae", NeoverseV2Model,
+def : ProcessorModel<"neoverse-v3ae", NeoverseV3AEModel,
                      ProcessorFeatures.NeoverseV3AE, [TuneNeoverseV3AE]>;
 def : ProcessorModel<"exynos-m3", ExynosM3Model, ProcessorFeatures.ExynosM3,
                      [TuneExynosM3]>;