merge main into amd-staging #413
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Now that llvm-libc has `nextafterf128`.
…#165260) Variable ops (VARIABLE/VARIABLE_READ/VARIABLE_WRITE) are part of the TOSA specification and should therefore be defined in `TosaOps.td`.
Test added in llvm#164905, skipped by llvm#165318, but that change did not guard the import. This import is run when we parse the file which happens before any skips are applied.
Factor out common code to determine legality of hoisting and sinking. The patch has the side-effect of fixing an underlying bug, where a load/store pair is reordered.
…lvm#149510) This patch adds a step to the MachineSMEABIPass that propagates desired ZA states. This aims to pick better ZA states for edge bundles, as when many (or all) blocks in a bundle do not have a preferred ZA state, the ZA state assigned to a bundle can be less than ideal. An important case is nested loops, where only the inner loop has a preferred ZA state. Here we'd like to propagate the ZA state from the inner loop to the outer loops (to avoid saves/restores in any loop).
Add the scheduling models for Neoverse V3 and Neoverse V3AE based on information taken from the V3 Software Optimization guide: https://developer.arm.com/documentation/109678/300/?lang=en and on information taken from the V3AE Software Optimization guide: https://developer.arm.com/documentation/109703/300/?lang=en Implements llvm#134977
This helps clean up some more legalization artefacts during legalization, in a similar way to other operations, and helps some of the DUP cases get through legalization successfully.
…r big (illegal) integer types (llvm#165361) Beginning of an investigation into how we can better handle bit twiddling of _BitInt types
…165364) This test passes with both plugins, but only ran with the DIA plugin. It was fixed with llvm#161678, where I missed this test.
) The Intel Cache Control tests are separated and not validated as `spirv-val` fails with: "ID '7' decorated with CacheControlLoadINTEL multiple times is not allowed". However, Intel extension does allow duplicated decoration if cache level in each annotation is different. It seems that `spirv-val` does not currently support it.
ptrtoaddr can be treated the same way as ptrtoint here.
For now not trying to share the code with ptrtoint, as there's very little code. Also fix IRBuilder::CreatePtrToAddr to actually create a PtrToAddr instruction...
dpalermo
approved these changes
Oct 28, 2025
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