[AIROCMLIR-466] Extend tuning db key with num_cu and num_chiplets#2248
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mirza-halilcevic merged 6 commits intodevelopfrom Feb 24, 2026
Merged
[AIROCMLIR-466] Extend tuning db key with num_cu and num_chiplets#2248mirza-halilcevic merged 6 commits intodevelopfrom
mirza-halilcevic merged 6 commits intodevelopfrom
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Pull request overview
This PR extends the tuning database key structure to include hardware-specific parameters (num_cu and num_chiplets) in addition to architecture and problem configuration. This enables more precise performance tuning by distinguishing entries based on the number of compute units and chiplets available on the GPU.
Changes:
- Extended tuning database key from (arch, config) to (arch, num_cu, num_chiplets, config)
- Updated parser to support three database formats: legacy (3 fields), v2 (4+ fields), and v3 (5+ fields)
- Modified all tuning database lookups and updates to use the new 4-tuple key structure
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Automated weekly review of merged PRs #2234 #2240 #2248 #2249 #2251 #2254 #2257 #2258 #2259 #2270 #2271. Identifies 6 areas with weak test coverage and meaningful business risk: 1. ConcurrentQueue (no unit tests, multi-threaded, silent deadlock risk) 2. parse_tuning_db_line / read_tuning_db key schema change (no Python tests) 3. BooleanElementwiseConverter missing f16/unsigned dtype coverage 4. Attention MaxNumFOp vs MaximumFOp NaN correctness (no dedicated test) 5. firstCausalMaskIter off-by-one risk (no non-trivial shape test) 6. Sliding window attention edge cases (windowSize=0/>=seqLen/unaligned) The GitHub discussion API returned FORBIDDEN (read-only CI token); analysis committed here as a permanent record. Co-authored-by: Djordje Antic <djordje.antic@amd.com>
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Motivation
In addition to architecture and problem config, use number of CUs and number of chiplets as keys into a tuning database.
Technical Details
Appropriate changes made to perfRunner.py.
Submission Checklist