Roch CPU 1.0.3

Highlights:

• CPU Core Voltage now updates the Renesas regulator and Intel OC mailbox together, with read-back, rollback protection, and measured Vcore verification.
• Adaptive Ring Voltage shows the real shared IA/core-rail value instead of Auto.
• CPU header now uses labeled fields, shows microcode, and formats cores / threads as requested.
• Removed the Revert button and updated the Intel screenshot and documentation.
• CPU E-Core L2 displays its programmed voltage target when present.

Download and extract Roch-CPU-1.0.3-win-x64.zip, then run Roch CPU.exe as administrator. Keep all files together. This self-contained x64 package needs no separate .NET runtime.

Roch CPU 1.0.2

Roch CPU 1.0.2 adds the shared YouTube | X | Discord footer and updated documentation, with .NET 10 builds and the compact CPU/memory tuning layout.

Download and extract Roch-CPU-1.0.2-win-x64.zip, then run Roch CPU.exe as administrator. Keep all driver and support files together. This self-contained x64 package needs no separate .NET runtime.

Controls depend on CPU, motherboard, BIOS and driver support. Optional PawnIO enables supported AMD power-table reads. Overclocking can cause instability or data loss.

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Roch CPU 1.0.1

Base clock and CPU VDD2 are settable now, and applying a change no longer freezes the window.

Base clock and CPU VDD2 — MSI 600/700-series boards

Neither comes from the CPU: one is a synthesiser on the board, the other a voltage regulator, and both sit on an I²C bus the embedded controller owns rather than on the PCH SMBus. Roch CPU reaches them through the mailbox that EC exposes.

• Base clock
• CPU VDD2, clamped to 1.100–1.450 V, where the raw byte reaches past 3 V and would take the memory controller with it

A wrong value on either does not produce a wrong reading, it stops the machine — so nothing is computed from an assumed zero point, the target is approached in small steps, and every step is measured: base clock against the ACPI timer, which does not move with it, VDD2 at the board. Anything that lands off target puts back the value found at start-up and stops.

There is no ceiling on base clock. Where a board gives up depends on the memory, the cache ratio and how far the CPU is already pushed, and only the person at the machine knows it. Base clock scales the memory controller, the ring and the PCIe/DMI reference together, so a little goes a long way and past a point the machine simply stops; above 105 MHz the window asks for confirmation, which stops a typo rather than a decision. The real limit is that a reading the meter cannot confirm is treated as a fault and rolled back, because past that point there is no way to know a write landed.

Read-only on other boards, as before.

Also in this release

• Apply and Reset run off the UI thread, so the window stays live while a change is measured
• Voltage rows re-read as the window refreshes; a single bad read at launch no longer sits on screen for the life of the process
• Fixed: the E-core L2 row could show Auto while that domain was in fact holding an override
• Fixed: the title bar's close and minimise buttons were being drawn with no glyph at all, so they were invisible
• --help lists the diagnostic switches. The EC probes that could hang the board are gone, along with the base-clock diagnostics written against a reading of the EC that turned out to be wrong
• Shorter README, and the archives now carry LICENSE and THIRD-PARTY-NOTICES.md

Downloads

• RochCPU-1.0.1-win-x64.zip needs the .NET 8 Desktop Runtime
• RochCPU-1.0.1-win-x64-selfcontained.zip runs without it

Run as administrator. Windows Memory Integrity (Core Isolation) or the vulnerable-driver blocklist can refuse the WinRing0 driver; the window says so when that happens.

Roch CPU 1.0.0

Roch CPU 1.0.0: board-independent CPU and memory tuning for Intel LGA1700 and AMD Ryzen. One dark window, typeable values, a log.

Intel (12th / 13th / 14th Gen, any 600/700-series board)

• CPU / E-core / ring ratios, the per-active-core turbo table, PL1 / PL2
• Core, E-core L2, ring, SA and GT voltage offsets and overrides through the OC mailbox, checked against the real Vcore the Super I/O measures
• DDR5 VDD / VDDQ / VPP on each DIMM's PMIC, calibrated against the PMIC's own ADC

AMD Ryzen (Zen 2 to Zen 5, AM4 / AM5)

• PPT, TDC, EDC and the thermal limit through the SMU mailbox
• PBO scalar, Curve Optimizer (all cores, plus a per-core window with read-back from the SMU), FMax
• PPT / TDC / EDC read back from the SMU power table when PawnIO is installed (the bundled WinRing0 cannot read it); otherwise the rows start as Auto and show what you wrote
• DDR5 VDD / VDDQ / VPP over the FCH SMBus, same calibration and safety as on Intel
• Validated on an MSI B850MPOWER with a Ryzen 7 9850X3D; the Zen 5 table layout, the stock-limit messages and the 10 mV VDDQ step on G.Skill kits were measured there

Downloads

• RochCPU-1.0.0-win-x64.zip needs the .NET 8 Desktop Runtime
• RochCPU-1.0.0-win-x64-selfcontained.zip runs without it

Run as administrator. Windows Memory Integrity (Core Isolation) can refuse the WinRing0 driver; the window says so.

The AMD path was written with Ivan Rusanov's ZenStates-Core as the reference for SMU mailboxes and message numbers; see THIRD-PARTY-NOTICES.md.