Roch Viewer 1.0.3

Roch Viewer 1.0.3 reorganizes Intel Timings and Training into compact two-column layouts while preserving Primary timings. It adds independent A1/B1 module readings, dedicated IMC and RTL views, expanded System Info, and snapshot voltage reporting.

The interface is now 750 × 775 px. Summary fits without scrolling, the utility buttons align with the main tabs, longer pages remain scrollable, and Graphics appears at the bottom of System Info.

Download RochViewer.exe. Obtain inpoutx64.dll separately from https://www.highrez.co.uk/downloads/inpout32/ and place it beside the executable, then run as administrator. The driver is not bundled. No Python or .NET installation is needed.

Readings depend on hardware, BIOS, and driver access. The tool is read-only.

Validation: all 1,323 tests passed (5 hardware-dependent tests skipped); the executable was built and packaged by GitHub Actions using Python 3.13.

SHA-256: C098F4D3EB962122F9CB6D1559CFA54F6FD7CC4658E77ABFAE1CE04D4567A535

Roch Viewer 1.0.2

Roch Viewer 1.0.2 refreshes the Summary and timing layouts with DRAM Ratio, voltage snapshots, compact per-channel timings, aligned row shading, and a red-bordered memory-module selector. Matching channel values display once; differences remain paired.

Includes native AMD preamble/postamble and ECC reporting, supported memory-training fields, tested board-specific VDDIO, per-DIMM details, and YouTube | X | Discord footer links. Graphics was removed from Telemetry; GPU identity remains in System Info.

Download RochViewer.exe. Obtain inpoutx64.dll separately from https://www.highrez.co.uk/downloads/inpout32/ and place it beside the executable, then run as administrator. The driver is not bundled. No Python or .NET installation is needed.

Readings depend on hardware, BIOS and driver access. The tool is read-only.

Validation: 1,278 tests run successfully (7 skipped); executable built with PyInstaller.

Roch Viewer 1.0.1

A read-only memory-controller and timing viewer for Windows. This is a
maintenance release: three wrong readings, a text dump, and an interface pass.

Fixed

CA/CS/CK ODT Group B printed "RFU". These rows decode RZQ over 0.5, 1, 2, 3,
4, 5 and 6, and the table carried RFU where the 48 Ω rung belongs: 480, 240,
120, 80, 60, RFU, 40 — every neighbour present and only that step missing. All
three Group B rows sit on that code, so all three reported a reserved setting
where a real termination was programmed. Group A was untouched because none of
its codes lands there.

The first diagnosis was wrong and looked better than the right one: read four
bits wide the field reads 14, which is exactly what firmware leaving a group
unprogrammed would look like on a board with one DIMM per channel — which this
is. The field is three bits.

VDD2 was blank. The Super I/O rail map was derived on a different MSI board
and is board-specific by its own warning. Index 4 of that sensor window is the
DRAM rail at 1.572 V there; here it is CPU VDD2 at 1.380 V, matching HWiNFO
exactly. Same chip, same address, different rail — so the map is chosen by board
model now. Carried across unchanged it would have printed VDD2's voltage under
the name DRAM.

VTT is gone on LGA 1700 DDR5. A Skylake-era board rail. The DDR4 row list
already said no LGA 1700 VRM or Super I/O channel reports one, which is a fact
about the socket rather than the memory generation; the DDR5 list was missing
it.

Added

A Dump button in the Advanced window, writing every row to
RochViewer.txt on the desktop as name : value — a configuration kept or
posted without screenshotting five tabs. The column is measured off a reference
tool's own dump so the two read side by side, the desktop is asked of Windows
rather than assumed (~/Desktop is wrong wherever OneDrive has redirected it),
and a row that could not be read is written N/A rather than dropped: a dump
that quietly omits what it missed is one you cannot trust to be complete.

A Board Revision row in System Info, moved out of the board name where it
had been appended.

Interface

Every hairline is one pixel and carries the brand red, muted so a one-pixel line
does not read heavier than it is. The dark surfaces all drop by the same six
values, so the steps between them are unchanged and only the floor moved. The
Summary's clock block gains the zebra shading the tables below it have. The
window title is plain text, leaving the red to mark what is selected.

The unit is spelled MHz throughout — it was Mhz in fifteen places and MHz
in twenty-three. Gear Mode reads 2 rather than Gear Mode 2 beside a label
already saying it. The processor loses its (R) and (TM).

Under it

The SMBIOS-only channel count assumed which Physical Memory N tags were
channel A and which channel B. No board is obliged to number its tags that way
and this one does not, so the channel letter is read off the socket locator now
— and a socket that reports itself empty no longer names a channel the board has
nothing in.

Removed, none of it referenced anywhere: _wmi_live, driver_available,
TEMPERATURE_BLOCK_START, the DFE_TAP_FORMULA table, four unused bank-group
constants and a duplicated CA_ODT_FORMULA. One fact that was written twice —
the Arrow Lake memory reference, as 33.334 in one getter and "133.33 Mhz" in
another — is one named constant, still derived rather than read, and the comment
says so.

Still true from 1.0.0

The driver is not distributed here. Download the InpOut32/64 binaries from
highrez.co.uk — the "Binaries
only" archive — and put inpoutx64.dll beside RochViewer.exe. Without it
the window still opens and every register-backed row reads N/A, and the program
says so rather than leaving you to guess. Installing it registers a permanent
Windows service; the 1.0.0 notes explain what that means and how to remove it.
Run as Administrator. The EXE is unsigned, so SmartScreen will prompt.

A row that reads nothing still shows nothing. No reading here is modelled,
estimated or filled in.

1258 tests, run on Windows for every push. GPL-3.0-or-later; the AMD backend
follows ZenStates-Core and ZenTimings by irusanov, see THIRD_PARTY_NOTICES.txt.

Roch Viewer 1.0.0

A read-only memory-controller and timing viewer for Windows. It reads what the
memory controller is actually doing and shows it beside the module's own SPD
and telemetry. It has no write path that changes a setting.

Before it will read anything

The low-level driver is not distributed here. Download the InpOut32/64
binaries from highrez.co.uk —
the "Binaries only" archive is enough — and put inpoutx64.dll beside
RochViewer.exe. That one file is the whole requirement: the kernel driver is
inside it as a resource, and the archive contains no .sys because it does not
need to.

Without it the window still opens and every register-backed row reads N/A — the
program says so in a strip across the top rather than leaving you to guess why
everything is empty.

Installing it is not just a file copy. The first elevated run writes the
embedded driver to System32\Drivers\inpoutx64.sys and registers it as an
automatic-start Windows service, which stays there afterwards whether or not
this program runs again.
Removing it means stopping and deleting the inpoutx64 service and deleting
that file — not deleting the folder you downloaded.

It is also no longer maintained upstream: its author says so on the download
page, and that he can no longer sign the driver. It works and it is signed, and
comparable tools depend on it or something like it, but nobody is fixing it.
Windows security software may object; decide for yourself whether you want it on
your machine.

Run as Administrator. The EXE is unsigned, so SmartScreen will prompt on first
run.

Platforms

Platform	Memory	Read from
LGA1700 / Alder & Raptor Lake	DDR5 or DDR4	Intel MCHBAR
LGA1851 / Arrow Lake	DDR5	Intel MCHBAR
AM5 / Granite Ridge	DDR5	AMD UMC, SMU and APOB

What it reads

• Primary, secondary and tertiary timings, refresh, command and power-down
  groups, both memory controllers in parallel columns.
• The electrical picture: RTT, ODT, RON, VREF levels, per-group drive strengths
  and slew compensation, ODT latencies, DFE taps.
• Per-channel read latencies, controller feature switches, ECS state, preambles,
  and the DDR5 mode registers.
• Module identity from the SPD5 hub, including on boards with SPD Write Disable
  armed.
• Live telemetry with minimum, maximum and average per reading: clocks,
  temperatures including the die's own, package and core power from the RAPL
  counters in MCHBAR, board rails, each DIMM's PMIC, the graphics card, and the
  count of hardware errors Windows has logged.

About "read-only"

It changes no setting, and the writes that exist are the ones a read cannot
happen without, each pinned to a fixed destination no caller can redirect:

• Selectors that choose what the next read returns — the PMIC's ADC channel
  and the SPD hub's page — each restored afterwards.
• The AMD SMU mailbox. Telemetry there is not memory-mapped: the SMU is
  asked for it, and asking means writing a message ID to the SMN data window.
  Four command IDs are permitted and every one is a query. No message that sets
  a limit, a voltage or a frequency is reachable, and the write-capable SMU
  diagnostics this project was developed with are deliberately absent from this
  repository.

Building it yourself

Everything needed is in the repository — the README has step-by-step
instructions for Python and the dependencies. The test suite is 1242 tests; CI
runs them on Windows for every push.

GPL-3.0-or-later. The AMD backend follows ZenStates-Core and ZenTimings by
irusanov; see THIRD_PARTY_NOTICES.txt.