Assembly Bite — ML Macromodel Corpus

Author: Ahmad Ali Parr
Trust: Bel Esprit D'Accord Irrevocable Trust · EIN 42-697643

Low-level pseudo-assembly language for representing ML models at the instruction level. Token matchers, tree matchers, full transformer macromodels with multiplicity — plus production SASS/PTX kernels for sm_89 (RTX 4090).

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What Is Assembly Bite

Assembly Bite is Ahmad's custom pseudo-assembly language for expressing ML model computations at the byte-code level. Four instruction types:

• .DATA — memory layout declarations (.word, .repl, .float)
• .CODE — instruction stream (LOAD, STORE, CALL, MATMUL, ADD, SUB, CMP, JEQ, etc.)
• Subroutine calls for primitive operations (MATMUL, SOFTMAX, RELU, LAYER_NORM, ADD_BIAS)
• No invented syntax — grounded in standard CS algorithms

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Contents

examples/
  token-matcher/token_matcher.asm     — Literal token ID sequence matcher (sliding window)
  tree-matcher/tree_matcher.asm       — DFS path matcher on [id, child, sibling] trees
  transformer/transformer_macromodel.asm — Full transformer: 24L × 12H × 768D × M=4

python/
  deberta_encoder.py                  — DeBERTa-v3 encoder wrapper + instruction token
  gguf_dag_pipeline.py                — GGUF load + networkx DAG pipeline

sass/
  flash_attention.ptx                 — Flash attention paged (sm_89 Hopper)
  dequant_q4k.ptx                     — GGUF Q4_K dequant PTX (sm_89)
  dequant_q4k.sass                    — GGUF Q4_K dequant SASS
  cuda_kernels.c                      — Host launch wrappers
  mamba_bind.h                        — Mamba SSM + GGUF binding header
  qemu_arm64_holyc.HC                 — HolyC QEMU ARM64 integration

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Transformer Macromodel — Multiplicity Architecture

The key insight in transformer_macromodel.asm: each neuron block has M copies (default M=4). The outer loop is L×A×M — layer × head × multiplicity. Each copy computes Q/K/V independently. Results are summed across copies before the next layer.

Parameters: L=24, A=12, D=768, H=3072, M=4
Weight layout: W_Q[L][A][M][D][D] = 24×12×4×768×768
Per copy: full attention + FFN + residual + layer norm
Aggregate: LAYER_ACC += LAYER_OUT for each M copy

This is distinct from standard multi-head attention — it's multiplicity within each head, not across heads.

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SASS/PTX Kernels — sm_89 (RTX 4090)

flash_attention.ptx

Full paged flash attention with TMA async copy and WMMA tensor core tiles.

dequant_q4k.ptx / dequant_q4k.sass

GGUF Q4_K block dequantization. 32-value blocks → FP16. Each thread processes 8 values (4 packed bytes). 36 bytes per block layout: [32 bytes packed][2 bytes scale][2 bytes min].

Grid: ceil(num_blocks / 256) blocks
Block: 256 threads
Dequant: q_val * scale + min → FP16

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Build

# PTX → Cubin (requires CUDA 12.x + SM89 GPU)
ptxas -arch=sm_89 sass/dequant_q4k.ptx -o dequant_q4k.cubin
ptxas -arch=sm_89 sass/flash_attention.ptx -o flash_attention.cubin

# Host wrappers
nvcc -arch=sm_89 sass/cuda_kernels.c -o kernels.so

# Python
pip install torch transformers llama_cpp_python networkx
python python/deberta_encoder.py

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© 2026 Bel Esprit D'Accord Irrevocable Trust · Patent Pending · θ = 89/2462