PR

.gitignore

@@ -88,3 +88,6 @@ GTAGS
 *.orig
 *~
 \#*#
+
+/oe-*
+bitbake-cookerdaemon.log

CONTRIBUTING.md

@@ -0,0 +1,30 @@
+# Contributing guide
+
+This document serves as a checklist before contributing to this repository. It includes links to read up on if topics are unclear to you.
+
+This guide mainly focuses on the proper use of Git.
+
+## 1. Issues
+
+STM32MPU projects do not activate "Github issues" feature for the time being. If you need to report an issue or question about this project deliverables, you can report them using [ ST Support Center ](https://my.st.com/ols#/ols/newrequest)  or  [ ST Community MPU Forum ](https://community.st.com/s/topic/0TO0X0000003u2AWAQ/stm32-mpus).
+
+## 2. Pull Requests
+
+STMicrolectronics is happy to receive contributions from the community, based on an initial Contributor License Agreement (CLA) procedure.
+
+* If you are an individual writing original source code and you are sure **you own the intellectual property**, then you need to sign an Individual CLA (https://cla.st.com).
+* If you work for a company that wants also to allow you to contribute with your work, your company needs to provide a Corporate CLA (https://cla.st.com) mentioning your GitHub account name.
+* If you are not sure that a CLA (Individual or Corporate) has been signed for your GitHub account you can check here (https://cla.st.com).
+
+Please note that:
+* The Corporate CLA will always take precedence over the Individual CLA.
+* One CLA submission is sufficient, for any project proposed by STMicroelectronics.
+
+__How to proceed__
+
+* We recommend to fork the project in your GitHub account to further develop your contribution. Please use the latest commit version.
+* Please, submit one Pull Request for one new feature or proposal. This will ease the analysis and final merge if accepted.
+
+__Note__
+
+Merge will not be done directly in GitHub but it will need first to follow internal integration process before public deliver in a standard release. The Pull request will stay open until it is merged and delivered.

MAINTAINERS

@@ -242,7 +242,9 @@ F:	drivers/misc/stm32mp_fuse.c
 F:	drivers/mmc/stm32_sdmmc2.c
 F:	drivers/phy/phy-stm32-usbphyc.c
 F:	drivers/pinctrl/pinctrl_stm32.c
+F:	drivers/power/pmic/stpmic1.c
 F:	drivers/power/regulator/stm32-vrefbuf.c
+F:	drivers/power/regulator/stpmic1.c
 F:	drivers/ram/stm32mp1/
 F:	drivers/misc/stm32_rcc.c
 F:	drivers/reset/stm32-reset.c

Makefile

@@ -3,7 +3,7 @@
 VERSION = 2018
 PATCHLEVEL = 11
 SUBLEVEL =
-EXTRAVERSION =
+EXTRAVERSION = -stm32mp-r4.2
 NAME =
 
 # *DOCUMENTATION*

README

@@ -2192,6 +2192,9 @@ The following options need to be configured:
 		CONFIG_SF_DEFAULT_MODE 		(see include/spi.h)
 		CONFIG_SF_DEFAULT_SPEED		in Hz
 
+		In case of DT boot, SPI don't read default speed and mode
+		from CONFIG_*, but from platdata values computed from available
+		DT node
 
 - TFTP Fixed UDP Port:
 		CONFIG_TFTP_PORT

arch/arm/Kconfig

@@ -1313,21 +1313,27 @@ config ARCH_STM32MP
 	select DM_GPIO
 	select DM_RESET
 	select DM_SERIAL
+	select ENV_VARS_UBOOT_RUNTIME_CONFIG
 	select MISC
 	select OF_CONTROL
 	select OF_LIBFDT
+	imply OF_LIBFDT_OVERLAY
+	select OF_SYSTEM_SETUP
 	select PINCTRL
 	select REGMAP
 	select SUPPORT_SPL
 	select SYSCON
 	select SYSRESET
+	select SYS_ARCH_TIMER
 	select SYS_THUMB_BUILD
 	imply CMD_DM
+	imply CMD_POWEROFF
 	help
 	  Support for STM32MP SoC family developed by STMicroelectronics,
 	  MPUs based on ARM cortex A core
-	  U-BOOT is running in DDR and SPL support is the unsecure First Stage
-	  BootLoader (FSBL)
+	  U-BOOT is running in DDR, loaded by the First Stage BootLoader (FSBL).
+	  FBSL can be TF-A: Trusted Firmware for Cortex A, for trusted boot chain.
+	  SPL is the unsecure FSBL for the basic boot chain.
 
 config ARCH_ROCKCHIP
 	bool "Support Rockchip SoCs"

arch/arm/cpu/armv7/arch_timer.c

@@ -49,6 +49,9 @@ unsigned long long get_ticks(void)
 
 ulong timer_get_boot_us(void)
 {
+	if (!gd->arch.timer_rate_hz)
+		timer_init();
+
 	return lldiv(get_ticks(), gd->arch.timer_rate_hz / 1000000);
 }
 

arch/arm/dts/Makefile

@@ -553,6 +553,8 @@ dtb-$(CONFIG_ARCH_ASPEED) += ast2500-evb.dtb
 dtb-$(CONFIG_ARCH_STI) += stih410-b2260.dtb
 
 dtb-$(CONFIG_TARGET_STM32MP1) += \
+	stm32mp157a-dk1.dtb \
+	stm32mp157c-dk2.dtb \
 	stm32mp157c-ed1.dtb \
 	stm32mp157c-ev1.dtb
 

arch/arm/dts/stm32429i-eval-u-boot.dtsi

@@ -92,57 +92,46 @@
 };
 
 &gpioa {
-	compatible = "st,stm32-gpio";
 	u-boot,dm-pre-reloc;
 };
 
 &gpiob {
-	compatible = "st,stm32-gpio";
 	u-boot,dm-pre-reloc;
 };
 
 &gpioc {
-	compatible = "st,stm32-gpio";
 	u-boot,dm-pre-reloc;
 };
 
 &gpiod {
-	compatible = "st,stm32-gpio";
 	u-boot,dm-pre-reloc;
 };
 
 &gpioe {
-	compatible = "st,stm32-gpio";
 	u-boot,dm-pre-reloc;
 };
 
 &gpiof {
-	compatible = "st,stm32-gpio";
 	u-boot,dm-pre-reloc;
 };
 
 &gpiog {
-	compatible = "st,stm32-gpio";
 	u-boot,dm-pre-reloc;
 };
 
 &gpioh {
-	compatible = "st,stm32-gpio";
 	u-boot,dm-pre-reloc;
 };
 
 &gpioi {
-	compatible = "st,stm32-gpio";
 	u-boot,dm-pre-reloc;
 };
 
 &gpioj {
-	compatible = "st,stm32-gpio";
 	u-boot,dm-pre-reloc;
 };
 
 &gpiok {
-	compatible = "st,stm32-gpio";
 	u-boot,dm-pre-reloc;
 };
 

arch/arm/dts/stm32f429-disco-u-boot.dtsi

@@ -87,57 +87,46 @@
 };
 
 &gpioa {
-	compatible = "st,stm32-gpio";
 	u-boot,dm-pre-reloc;
 };
 
 &gpiob {
-	compatible = "st,stm32-gpio";
 	u-boot,dm-pre-reloc;
 };
 
 &gpioc {
-	compatible = "st,stm32-gpio";
 	u-boot,dm-pre-reloc;
 };
 
 &gpiod {
-	compatible = "st,stm32-gpio";
 	u-boot,dm-pre-reloc;
 };
 
 &gpioe {
-	compatible = "st,stm32-gpio";
 	u-boot,dm-pre-reloc;
 };
 
 &gpiof {
-	compatible = "st,stm32-gpio";
 	u-boot,dm-pre-reloc;
 };
 
 &gpiog {
-	compatible = "st,stm32-gpio";
 	u-boot,dm-pre-reloc;
 };
 
 &gpioh {
-	compatible = "st,stm32-gpio";
 	u-boot,dm-pre-reloc;
 };
 
 &gpioi {
-	compatible = "st,stm32-gpio";
 	u-boot,dm-pre-reloc;
 };
 
 &gpioj {
-	compatible = "st,stm32-gpio";
 	u-boot,dm-pre-reloc;
 };
 
 &gpiok {
-	compatible = "st,stm32-gpio";
 	u-boot,dm-pre-reloc;
 };
 

arch/arm/dts/stm32f469-disco-u-boot.dtsi

@@ -92,57 +92,46 @@
 };
 
 &gpioa {
-	compatible = "st,stm32-gpio";
 	u-boot,dm-pre-reloc;
 };
 
 &gpiob {
-	compatible = "st,stm32-gpio";
 	u-boot,dm-pre-reloc;
 };
 
 &gpioc {
-	compatible = "st,stm32-gpio";
 	u-boot,dm-pre-reloc;
 };
 
 &gpiod {
-	compatible = "st,stm32-gpio";
 	u-boot,dm-pre-reloc;
 };
 
 &gpioe {
-	compatible = "st,stm32-gpio";
 	u-boot,dm-pre-reloc;
 };
 
 &gpiof {
-	compatible = "st,stm32-gpio";
 	u-boot,dm-pre-reloc;
 };
 
 &gpiog {
-	compatible = "st,stm32-gpio";
 	u-boot,dm-pre-reloc;
 };
 
 &gpioh {
-	compatible = "st,stm32-gpio";
 	u-boot,dm-pre-reloc;
 };
 
 &gpioi {
-	compatible = "st,stm32-gpio";
 	u-boot,dm-pre-reloc;
 };
 
 &gpioj {
-	compatible = "st,stm32-gpio";
 	u-boot,dm-pre-reloc;
 };
 
 &gpiok {
-	compatible = "st,stm32-gpio";
 	u-boot,dm-pre-reloc;
 };
 

arch/arm/dts/stm32f746.dtsi

@@ -130,7 +130,6 @@
 			gpioa: gpio@40020000 {
 				gpio-controller;
 				#gpio-cells = <2>;
-				compatible = "st,stm32-gpio";
 				reg = <0x0 0x400>;
 				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOA)>;
 				st,bank-name = "GPIOA";
@@ -140,7 +139,6 @@
 			gpiob: gpio@40020400 {
 				gpio-controller;
 				#gpio-cells = <2>;
-				compatible = "st,stm32-gpio";
 				reg = <0x400 0x400>;
 				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOB)>;
 				st,bank-name = "GPIOB";
@@ -151,7 +149,6 @@
 			gpioc: gpio@40020800 {
 				gpio-controller;
 				#gpio-cells = <2>;
-				compatible = "st,stm32-gpio";
 				reg = <0x800 0x400>;
 				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOC)>;
 				st,bank-name = "GPIOC";
@@ -161,7 +158,6 @@
 			gpiod: gpio@40020c00 {
 				gpio-controller;
 				#gpio-cells = <2>;
-				compatible = "st,stm32-gpio";
 				reg = <0xc00 0x400>;
 				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOD)>;
 				st,bank-name = "GPIOD";
@@ -171,7 +167,6 @@
 			gpioe: gpio@40021000 {
 				gpio-controller;
 				#gpio-cells = <2>;
-				compatible = "st,stm32-gpio";
 				reg = <0x1000 0x400>;
 				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOE)>;
 				st,bank-name = "GPIOE";
@@ -181,7 +176,6 @@
 			gpiof: gpio@40021400 {
 				gpio-controller;
 				#gpio-cells = <2>;
-				compatible = "st,stm32-gpio";
 				reg = <0x1400 0x400>;
 				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOF)>;
 				st,bank-name = "GPIOF";
@@ -191,7 +185,6 @@
 			gpiog: gpio@40021800 {
 				gpio-controller;
 				#gpio-cells = <2>;
-				compatible = "st,stm32-gpio";
 				reg = <0x1800 0x400>;
 				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOG)>;
 				st,bank-name = "GPIOG";
@@ -201,7 +194,6 @@
 			gpioh: gpio@40021c00 {
 				gpio-controller;
 				#gpio-cells = <2>;
-				compatible = "st,stm32-gpio";
 				reg = <0x1c00 0x400>;
 				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOH)>;
 				st,bank-name = "GPIOH";
@@ -211,7 +203,6 @@
 			gpioi: gpio@40022000 {
 				gpio-controller;
 				#gpio-cells = <2>;
-				compatible = "st,stm32-gpio";
 				reg = <0x2000 0x400>;
 				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOI)>;
 				st,bank-name = "GPIOI";
@@ -221,7 +212,6 @@
 			gpioj: gpio@40022400 {
 				gpio-controller;
 				#gpio-cells = <2>;
-				compatible = "st,stm32-gpio";
 				reg = <0x2400 0x400>;
 				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOJ)>;
 				st,bank-name = "GPIOJ";
@@ -231,7 +221,6 @@
 			gpiok: gpio@40022800 {
 				gpio-controller;
 				#gpio-cells = <2>;
-				compatible = "st,stm32-gpio";
 				reg = <0x2800 0x400>;
 				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOK)>;
 				st,bank-name = "GPIOK";