WaveBench v0.4.0
WaveBench v0.4.0 - arbitrary waveform closure / 任意波形闭环
WaveBench v0.4.0 closes the first real arbitrary-waveform loop for the RIGOL DG4202 and R&S RTM2032 lab pair.
WaveBench v0.4.0 为 RIGOL DG4202 与 R&S RTM2032 这套实验仪器组合打通了第一条真实的任意波形闭环。
The scope of this release is deliberately small: take a CSV/NPY waveform, validate and map it into DG4000/DG4202 14-bit DAC data, upload it through DATA:DAC VOLATILE, capture the result with RTM2032, and preserve enough evidence to decide whether the loop actually worked.
本次发布的范围刻意收窄:读取 CSV/NPY 波形,校验并映射为 DG4000/DG4202 14-bit DAC 数据,通过 DATA:DAC VOLATILE 上传,用 RTM2032 采集结果,并保留足够证据来判断这条回路是否真正跑通了。
Highlights / 亮点
- Added DG4202 arbitrary waveform upload through
DATA:DAC VOLATILE. - 新增 DG4202 任意波形上传功能,通过
DATA:DAC VOLATILE实现。 - Added raw byte transport support with
InstrumentTransport.write_bytes()and PyVISAwrite_raw. - 新增原始字节传输支持,通过
InstrumentTransport.write_bytes()和 PyVISAwrite_raw实现。 - Added DG4000/DG4202 14-bit DAC binary block generation from validated CSV / NPY waveforms.
- 新增从校验后的 CSV / NPY 波形生成 DG4000/DG4202 14-bit DAC 二进制块的功能。
- Promoted
source arb-loadfrom dry-run-only payload validation to a minimal upload command. - 将
source arb-load从仅 dry-run 的负载校验提升为可实际上传的最小命令。 - Added
source.arb_loadrun-plan step so upload, output enablement, capture, and[steps.expect]checks can live in one explicit plan. - 新增
source.arb_loadrun-plan 步骤,使上传、输出使能、采集和[steps.expect]检查能共存于一个显式计划中。 - Recorded the first real closure evidence: DG4202 triangle arbitrary waveform -> RTM2032 capture -> FFT peak at 1 kHz -> static report.
- 记录了首条真实闭环证据:DG4202 三角任意波形 → RTM2032 采集 → 1 kHz FFT 峰值 → 静态报告。
CLI example / 命令行示例
Dry-run validation remains available:
Dry-run 校验仍然可用:
python -m wavebench source arb-load \
--channel 1 \
--file waveform.npy \
--name REI_ARB \
--amplitude 1.0 \
--offset 0.0 \
--export-payload data/arb/REI_ARB.json \
--dry-runUpload requires an explicit playback frequency:
上传需指定回放频率:
python -m wavebench source arb-load \
--config wavebench.toml \
--channel 1 \
--file waveform.npy \
--name REI_TRI \
--amplitude 1.0 \
--frequency 1000 \
--offset 0.0 \
--output-onRun-plan example / Run-plan 示例
[[steps]]
kind = "source.arb_load"
channel = 1
file = "data/arb/triangle_1024.npy"
frequency_hz = 1000
amplitude_vpp = 1.0
offset_v = 0.0
output_on = true
[[steps]]
kind = "scope.capture"
channel = 1
label = "arb_triangle_1k"
window_frequency_hz = 1000
target_cycles = 10
target_vpp = 1.0
screenshot = true
[steps.expect]
voltage_vpp_v = { min = 0.8, max = 1.2 }
frequency_estimate_hz = { min = 950, max = 1050 }Validation / 验证
python -m pytest -q->150 passedgit diff --check-> OK- Lab closure record / 实验室闭环记录:
doc/project/WaveBench_v0.4_闭环验证记录.md
Not included / 未包含
v0.4.0 is not an arbitrary-waveform editor. It does not add GUI editing, cross-vendor waveform abstraction, non-volatile waveform library management, RAF / Ultra Station workflows, or automatic waveform synthesis.
v0.4.0 不是一个任意波形编辑器。它不包含 GUI 编辑、跨厂商波形抽象、非易失波形库管理、RAF / Ultra Station 工作流,也不包含自动波形合成。
Those can come later. This release is about proving the first small loop.
这些可以以后再做。本次发布的意义在于证明第一条小回路是可行的。