feat: v0.17.0 zone simulator — timing-realistic controller for SiL/HIL - #22
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Ports cpp-RCP's sim.hpp: a full rcp_controller_t implementation (not a
decorator, like mock.h) purpose-built for SiL/HIL testing, adding
configurable latency (constant or jitter via a seeded xorshift32 PRNG --
C99 has no <random>, and MSVC lacks POSIX's rand_r(), so a small
self-contained generator avoids both), fault injection
(rcp_sim_controller_fault()/_recover()), periodic Status publishing, and
watchdog-miss detection to validate the safety mechanisms from
v0.11.0-v0.16.0 (watchdog, deadline, powerstate, e2e, prioqueue, ratelimit).
Deviation from cpp-RCP: its watchdog-miss detector runs a background thread
that periodically refreshes a cached wd_miss_ atomic bool. This port
instead computes the miss state on demand in
rcp_sim_controller_watchdog_missed() directly from the last-kick timestamp
-- always accurate, with no polling-interval staleness window. The
background watchdog thread is still spawned (an otherwise-inert responsive
sleep loop) so close() still has a second thread to join, preserving the
"status and watchdog background threads" plural wording of REQ-SIM-008.
The per-subscription watcher-thread pattern and the publish/close
subs-array-stealing technique are both reused verbatim from mock.c's
established design, applied to sim.c's own struct.
tests/test_sim.c ports all 8 of cpp-RCP's test_sim.cpp cases.
Verification performed:
- Full test suite: 18/18 passing (added rcp_sim); 20 repeated local runs
of test_sim alone (debug + 20x ASan/UBSan) with no flakes.
- cfusa trace --req-coverage 100: Metric 2 100% (169/169, hard gate).
- cfusa check/lint: only known/ticketed CFUSA-L004 false positives
(SoundMatt/c-FuSa#59, DISP-0001), unchanged count (3).
- cfusa analyze/cyber/qualify/vuln: clean (0 errors).
- ASan/UBSan build+test pass: clean, no leaks/UB/races detected.
Signed-off-by: Matt <matt@jellybaby.com>
Signed-off-by: Matt Jones <47545907+SoundMatt@users.noreply.github.com>
This was referenced Aug 7, 2026
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Summary
sim.hpp: a fullrcp_controller_timplementation (not a decorator, likemock.h) purpose-built for SiL/HIL testing — configurable latency (constant or jitter via a seededxorshift32PRNG), fault injection, periodic Status publishing, and watchdog-miss detection.close()has a second thread to join, preserving REQ-SIM-008's "status and watchdog background threads" wording.mock.c's established design.tests/test_sim.cports all 8 of cpp-RCP'stest_sim.cppcases.Test plan
ctest --test-dir build— 18/18 passing (addedrcp_sim); 20 repeated local runs (debug + 20x ASan/UBSan) with no flakescfusa trace --req-coverage 100— Metric 2 100% (hard gate)cfusa check/lint— only known/ticketed CFUSA-L004 false positives (CFUSA-L004 recursion-check fires on virtually every function (false positive) c-FuSa#59, DISP-0001), unchanged countcfusa analyze/cyber/qualify/vuln— clean (0 errors)Signed-off-by: Matt matt@jellybaby.com