Pinout for SD card
The SPI interface in the FPGA seems to work well. The SPI clock is 50MHZ/8 = 6.25MHz.
| Address | Size | Read/Write | Description |
|---|---|---|---|
| FF30 | Byte | Write | Write to this address latches and transmits the byte |
| FF30 | Byte | Read | Reads return the contents of the receive shift register |
| FF32 | Byte | Write | 1 bit register. LSB controls directly the chip select line. |
| FF32 | Byte | Read | Status register. Bit 0 (LSB) returns the value written to chip select. Bit 1 is high if the SPI interface is still transferring data |
Chip select handling is easy:
* CS active:
clr @>FF32
* CS inactive:
seto @>FF32
The SPI interface at 6MHz is so fast, and the TMS9995 so slow, that in practice it is never necessary to check bit 1 of status register. Basically the only instruction sequence that reads the data before it is ready is the following:
LI R5,>FF30 ; Point to SPI
LI R6,>FFFF ; FF data to be sent
MOVB R6,*R5 ; Send FF
MOVB *R5,R7 ; Read receive shift register to R7
In the above the last instruction MOVB *R5,R7 will read data before it is ready if the system is running with zero wait states and workspace is in internal SRAM. Inserting a NOP instruction before the read fixes this.
Firmware is under development. The goal is to be able to boot from FAT filesystem.
As of 2016-04-16 reading of partition table, boot sector decoding and root directory printing and decoding all work. Missing piece is just the ability to actually read a given file.
Below is the pinout of SD card using www.etteam.com SD breakout board.
Wiring done EP 2016-04-08
| SD PIN | FPGA PIN | FUNCTION |
|---|---|---|
| 1 | 87 | CS |
| 2 | 88 | DI - Data to SD card |
| 5 | 84 | CLK |
| 7 | 85 | DO - Data out from SD |
Below is a first run from the firmware under development. Here the code reads the MBR into memory using option '3' and then returns back to menu. Going from there to EVMBUG allows one to see what was read. Data starts from offset 446 (>1BE) as it should! That is in memory at 85BE below.
