Hi,
I am a starter in this code and would like to initially change some Naxriscv instructions.
To provide some context, I was able to successfully compile and run litex, flash the board, and even boot Linux using Naxriscv as below:
python3 -m litex_boards.targets.digilent_nexys_video --cpu-type=naxriscv --bus-standard axi-lite --with-video-framebuffer --with-spi-sdcard --with-ethernet --xlen=64 --scala-args='rvc=true,rvf=true,rvd=true' --build --load
All good, thanks for those.
It seems that a way to change via changing the files located at pythondata/verilog/ext/NaxRiscv/src/main/scala/naxriscv/riscv because there are *.scala files and for example, the Rvi.scala file has the definitions of the instructions. Am I correct?
Let's say that the following is possible: I want to remove one of the instructions (e.g. AMOADD) generate a riscv without this instruction. Let's say I comment all *.scala files in this folder and related usage.
What is the command I have to use to regenerate the bitstream?
I am not sure, but it seems that I have to add --scala-file=.../python-cpu-naxriscv/verilog/configs gen.scala to the command above? Anyway, it seems that if I do that that it still uses the verilog files (under verilog folder) and not the *.scala files I meant before.
Any help is more than welcome!
Thanks much
Hi,
I am a starter in this code and would like to initially change some Naxriscv instructions.
To provide some context, I was able to successfully compile and run litex, flash the board, and even boot Linux using Naxriscv as below:
python3 -m litex_boards.targets.digilent_nexys_video --cpu-type=naxriscv --bus-standard axi-lite --with-video-framebuffer --with-spi-sdcard --with-ethernet --xlen=64 --scala-args='rvc=true,rvf=true,rvd=true' --build --load
All good, thanks for those.
It seems that a way to change via changing the files located at pythondata/verilog/ext/NaxRiscv/src/main/scala/naxriscv/riscv because there are *.scala files and for example, the Rvi.scala file has the definitions of the instructions. Am I correct?
Let's say that the following is possible: I want to remove one of the instructions (e.g. AMOADD) generate a riscv without this instruction. Let's say I comment all *.scala files in this folder and related usage.
What is the command I have to use to regenerate the bitstream?
I am not sure, but it seems that I have to add --scala-file=.../python-cpu-naxriscv/verilog/configs gen.scala to the command above? Anyway, it seems that if I do that that it still uses the verilog files (under verilog folder) and not the *.scala files I meant before.
Any help is more than welcome!
Thanks much